Subscribed Libraries
Electrical Electrical e-paper
Total: 694
| Sn | Title | Author | Abstract | Full Text |
|---|---|---|---|---|
| 641 | A Review on Charge Pump Circuits for PLL Applications | D. Shekhar, A. Raman | Abstract | Full Text |
| 642 | Implementation and Analysis of 32-bit pipelined RISC Processor Architecture | P. Indira, M. Kamaraju | Abstract | Full Text |
| 643 | Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology | Bharat H. Nagpara | Abstract | Full Text |
| 644 | Design of 8 Bit High Speed Pipelined ADC | Shivani R. Patel, Priyesh P. Gandhi | Abstract | Full Text |
| 645 | Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor | Nishtha K. Patel, Nilesh D. Patel | Abstract | Full Text |
| 646 | Characterization of High Performance Third Generation Current Conveyor using CMOS Technology | Megha M. Patel, Nilesh D. Patel | Abstract | Full Text |
| 647 | Automated Access Backdoor for UVM_REG Layer | Seep Sethi, Neeraj Kr. Shukla | Abstract | Full Text |
| 648 | Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave | Pragya Sharma, Neeraj Kr. Shukla, Rakhi Nangia | Abstract | Full Text |
| 649 | Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style | Megha Hulkey, Harshvardhan Upadhyay | Abstract | Full Text |
| 650 | Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating | J. Sudhakar, A. Mallikarjuna Prasad, Ajit Kumar Panda | Abstract | Full Text |
| 651 | A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier | Kirti Sharma, Anushree . | Abstract | Full Text |
| 652 | 4-Bit Magnitude Comparator Design using Different Logic Styles | Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary | Abstract | Full Text |
| 653 | Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter | Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav | Abstract | Full Text |
| 654 | Comparative Analysis of High Speed Comparator for A to D Converters | Priyesh Gandhi, Neha B. Rathod, N. M. Devashrayee | Abstract | Full Text |
| 655 | Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology | A.K. Pathrikar, Rajkumar S. Deshpande | Abstract | Full Text |
| 656 | Characterization of High Speed Phase Frequency Detector Circuit | Nilesh D. Patel, Amisha P. Naik | Abstract | Full Text |
| 657 | Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications? | Manisha Guduri, Vivek Kumar Agarwal, Aminul Islam | Abstract | Full Text |
| 658 | Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System | Moumita Acharya, Shreedeep Gangopadhyay | Abstract | Full Text |
| 659 | Optimized AES Implementation on Leon3 | Ashish Mishra, Sanal Kumar, Jaldeep Vasavada, Kota Solomon Raju | Abstract | Full Text |
| 660 | Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique | Prashant Gupta, Shashank Kumar Ranu, Manish Kumar Pandey, Aminul Islam | Abstract | Full Text |
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