Subscribed Libraries
Electrical Electrical e-paper
Total: 694
| Sn | Title | Author | Abstract | Full Text |
|---|---|---|---|---|
| 661 | Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology | Prateek Asthana, Sangeeta Mangesh | Abstract | Full Text |
| 662 | Designing of GaAs Based Resonant Tunneling Diode and Nano Scale Applications with Considering NEGF | Mehedi Hasan, Md. Kamrul Hassan, M. Tanseer Ali | Abstract | Full Text |
| 663 | A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions | Pratiksha Kharat | Abstract | Full Text |
| 664 | A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network | Abhishek Sharma, Sudhir Kumar Sharma | Abstract | Full Text |
| 665 | Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier | Athira A D, Anjaly Krishnan | Abstract | Full Text |
| 666 | Performance Analysis of CMOS and FinFET Based SRAM | Jeny Elsa Joji, Sreekala K. S., Dhanusha P. B. | Abstract | Full Text |
| 667 | Design, Verification and Circuit Level Implementation of a Ballistic MOSFET | Arun Kumar Chatterjee, B. Prasad | Abstract | Full Text |
| 668 | An Area Delay Optimized Carry-Select Adder | Sareeka Tulshiram Deore | Abstract | Full Text |
| 669 | Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter | Jalaja S., Vijaya Prakash A. M | Abstract | Full Text |
| 670 | A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault | Ram Vishnu S, Yasodha T | Abstract | Full Text |
| 671 | Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits | M. Balal Siddiqui, M. T. Beg, S. Naseem Ahmad | Abstract | Full Text |
| 672 | A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing | Radhika M. Somani, H. R. Upadhyay, K. Sujatha | Abstract | Full Text |
| 673 | Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime | Tarun Kumar Sachdeva, S. K. Agarwal, Alok K. Kushwaha | Abstract | Full Text |
| 674 | A Review on FPGA Parallel Architecture for Object Detection | Sudhir Dagar, Geeta Nijhawan | Abstract | Full Text |
| 675 | Comparative Analysis of Different SRAM Cells Architecture at 70 nm | Nidhi Tiwari, Vaibhav Neema, Kamal J. Rangra, Yogesh Chandra Sharma | Abstract | Full Text |
| 676 | Characterization of Low Power-Low Jitter Digital PLL | Nilesh D. Patel, Amisha P. Naik | Abstract | Full Text |
| 677 | Design of Three-Stage Pipelined Floating Point Arithmetic Operators | Shaikh Shoaib Arif, B. B. Godbole | Abstract | Full Text |
| 678 | High Gain Antenna Array (2x1 and 4x1) Design for WLAN Application | Devendra Sharma, Charanjeet Singh | Abstract | Full Text |
| 679 | Review Paper To Design a Low Power CNTFET Based XOR Gate | Veski Dabas, Surender Kumar Grewal | Abstract | Full Text |
| 680 | Review Paper: Low Power SRAM Cell using FinFET Technology | Mamta ., Surender Kumar Grewal | Abstract | Full Text |
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