Subscribed Libraries
Electrical Electrical e-paper
Total: 694
| Sn | Title | Author | Abstract | Full Text |
|---|---|---|---|---|
| 621 | Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder | Ankit Mitra | Abstract | Full Text |
| 622 | Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression | M. Viji, S. Chitra | Abstract | Full Text |
| 623 | Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor | Mujeeb Ulla Jeelani, Venkatesh Kumar N., Anoop S. Shandilya | Abstract | Full Text |
| 624 | Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects | Balaji B. S. | Abstract | Full Text |
| 625 | A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFETΓÇÖs Threshold Voltage Extractor | Anil K. Saini, Megha Agarwal | Abstract | Full Text |
| 626 | A New High Speed Low Power 1 Bit Full Adder | Angshuman Chakraborty, Sambhu Nath Pradhan | Abstract | Full Text |
| 627 | A High Performance Reference Circuit with Optimized Input Offset Operational Amplifier using Device Mismatch Model | Anil K. Saini, Kapil K. Rajput, Sanjay Singh, Ravi Saini | Abstract | Full Text |
| 628 | Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology | Lalita Machhindra Landge, Usha Jadhav | Abstract | Full Text |
| 629 | Performance Analysis of DNA Sequencing Using Smith-Waterman Algorithm on FPGA | Anna Hakim, Anam Kashtwari, Rajinder Tiwari, Jamini Sharma | Abstract | Full Text |
| 630 | Design of Energy Efficient Clock System | Rupali Ashok Walunj, S.D. Pable, G.K. Kharate | Abstract | Full Text |
| 631 | Reusable FM0/Manchester Encoding Using QCA | Harshada Dayanand Malage, Usha Jadhav | Abstract | Full Text |
| 632 | Near Field Wireless Powering of Implantable Devices | Simi P Thomas, Aparna Jose | Abstract | Full Text |
| 633 | Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits | Karishma Yadav, Vandana Khanna, Gaurav Shingwani, Ishita Ishita | Abstract | Full Text |
| 634 | Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications | Rupali Ashok Walunj, Sachin Dattatraya Pable, Gajanan Kashiram Kharate | Abstract | Full Text |
| 635 | Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode | Vandana Khanna, Srishti Singhal, Sushant Nagpal | Abstract | Full Text |
| 636 | Design and Implementation of an Efficient Ternary Control Unit | Satish S. Narkhede, BS Chaudhari, GK Kharate | Abstract | Full Text |
| 637 | Memristor Modelling for Common Source Amplifier Using 180 nm Technology | Herman Al Ayubi, Navaid Z. Rizvi, Piyush Kumar Mishra | Abstract | Full Text |
| 638 | Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology | Nishant Poras, Priyanka Goyal | Abstract | Full Text |
| 639 | CMOS Gm-C IF Filter using SCA for Dual Band Receiver | Kehul A. Shah, NM Devashrayee | Abstract | Full Text |
| 640 | All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey | Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta | Abstract | Full Text |
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