Subscribed Libraries
Electrical Electrical e-paper
Total: 694
| Sn | Title | Author | Abstract | Full Text |
|---|---|---|---|---|
| 541 | A Novel Approach Based On-Chip High Speed Optical Interconnection Network | abhishek sharma, sudhir kumar sharma, pramod sharma | Abstract | Full Text |
| 542 | Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with Left Handed Metamaterial | ram kishor sharma, mahendra kumar pandey, sandeep kumar agrawal | Abstract | Full Text |
| 543 | Implementation of Carry Select Adder with Reduced Area Scheme | pinaki satpathy | Abstract | Full Text |
| 544 | A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure | ajoy kumar khan | Abstract | Full Text |
| 545 | Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers | akash I mewan, N M Devashrayee | Abstract | Full Text |
| 546 | Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform | pradeep C bhaskar, prachi S gosavi | Abstract | Full Text |
| 547 | Design of High-Speed and Low-Power Carry Skip Adder | gutlapalli venkatrao, motkuri krishna | Abstract | Full Text |
| 548 | A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique | B S Patro, srinibasa padhy, monica swain, J K Das | Abstract | Full Text |
| 549 | Survey of System-on-Chip Modular Test Approach | harpreet vohra, amardeep singh | Abstract | Full Text |
| 550 | Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications | ankush chunn, rakesh kumar sareen | Abstract | Full Text |
| 551 | VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter | minakshi m wanjari, pankaj agrawal, ravindra kashirsagar | Abstract | Full Text |
| 552 | Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy | shashank gautam, pramod sharma | Abstract | Full Text |
| 553 | Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier | saguna goel, sakshi bajaj, amanpreet kaur | Abstract | Full Text |
| 554 | Design of FPGA Based ALU Using Reversible Logic Gates | vishal A Wankhede, ramprasad M gawande | Abstract | Full Text |
| 555 | Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog | ashima gandhi, neeraj kr. shukla | Abstract | Full Text |
| 556 | Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC | jatin A. jalal, mehul L Patel | Abstract | Full Text |
| 557 | Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power | Vijay Savani, N M Devashrayee | Abstract | Full Text |
| 558 | A New TGC-Differential Input Stage to Modify Dynamic Comparator | anurag sharma, gurinderpal singh | Abstract | Full Text |
| 559 | Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM | ashima gandhi, neeraj kr. shukla | Abstract | Full Text |
| 560 | Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique | archana kumari, navdeep prashar | Abstract | Full Text |
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