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Current Issue

International Journal of VLSI Circuit Design & Technology

Editors Overview

ijvcdt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

Current

Vol-01 Issue-02 2023

Regular Issue  Subscription Original Research Published on :- 04-Dec-2023

Implementation of Adders Using Ternary Based Multiple Valued Logic
M. Mani Kumari, K. Aishwarya, B. Sukruthi
Keywords: Ternary, MVL, CSKA, CSLA, RCA, HDL


Regular Issue  Subscription Original Research Published on :-

Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation
Malyadri Paduchur, [email protected]
Keywords: Gabor filter, image processing, MAC unit, sizing compilation, memory optimization, control unit, Xilinx, and Verilog HDL


Regular Issue  Subscription Original Research Published on :- 10-Jan-2024

Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Kalvala Shylaja, M. Satya Narayana
Keywords: Full adder, CSA, compressors, comparators, parity checkers


Regular Issue  Subscription Original Research Published on :- 21-Dec-2023

Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Vannala Bhavya, K. Shyamala Murthi
Keywords: CMOS, PMOS, NMOS, BSIM4 Model, Leakage current