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International Journal of VLSI Circuit Design & Technology Cover

International Journal of VLSI Circuit Design & Technology

Editors Overview

ijvcdt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.


Mr. AnganiChandra Sekhar.

Assistant Professor
GITAM Institute of Science
Editor in Chief
International Journal of VLSI Circuit Design & Technology
Email :


Publisher

STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd. A-118, 1st Floor, Sector-63, Noida, U.P. India, Pin – 201301
E-mail: [email protected]
(Tel) (+91) 0120- 4781 200
(Mob) (+91) 9810078958, +919667725932

About the Journal

International Journal of VLSI Circuit Design & Technology (ijvcdt) is a peer-reviewed hybrid open-access journal launched in 2023 that broadly covers the current, View Full Focus and Scope…

Journal Particulars

Title
International Journal of VLSI Circuit Design & Technology
Journal Abbreviation
ijvcdt
Issues Per Year (Frequency)
2 Issues (Jan-June),(July-Dec)
Publisher
STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd.
DOI
10.37591/IJVCDT
Copyright
STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd.
Starting Year
2023
Subject
Electronics & Telecommunication Engineering
Language
English
Publication Format
Hybrid Open Access
Type of Publication
Peer-reviewed Journal (Refereed Journal)
Website
https://journals.stmjournals.com/ijvcdt
Address
STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd. A-118, 1st Floor, Sector-63, Noida, U.P. India, Pin – 201301

Indexing
Google Scholar

Principal Contact
Pooja Kumari

[email protected]

1204746104

Latest Article

Vol-01 Issue-02 2023

Regular Issue  Subscription Original Research Published on :- December 4, 2023

Implementation of Adders Using Ternary Based Multiple Valued Logic
M. Mani Kumari, K. Aishwarya, B. Sukruthi
Keywords: Ternary, MVL, CSKA, CSLA, RCA, HDL

Regular Issue  Subscription Original Research Published on :- January 5, 2024

Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Vannala Bhavya, K. Shyamala Murthi
Keywords: CMOS, PMOS, NMOS, BSIM4 Model, Leakage current

Regular Issue  Subscription Original Research Published on :- January 10, 2024

Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Kalvala Shylaja, M. Satya Narayana
Keywords: Full adder, CSA, compressors, comparators, parity checkers

Regular Issue  Subscription Original Research Published on :- February 12, 2024

Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation
Malyadri Paduchur, [email protected]
Keywords: Gabor filter, image processing, MAC unit, sizing compilation, memory optimization, control unit, Xilinx, and Verilog HDL

Special Issue

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