64 Bit ALU DESIGN USING VEDIC MATHEMATHICS

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This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.

Year : 2026 | Volume : 04 | 01 | Page :
    By

    Sirigineedi Mounisha,

  • Uppalapati Joshna Venkata Srujana,

  • Vemula Rajesh,

  • Velugubanti Lakshman,

  • Yepuganti Manikanta,

  • I.Rama Satya.Nageswara Rao,

  • Saran Kumar,

  1. UG Student, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India
  2. UG Student, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India
  3. UG Student, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India
  4. UG Student, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India
  5. UG Student, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India
  6. Assistant Professor, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India
  7. Associate Professor, Department of ECE, Bonam Venkata Chalamayya Engineering College(A), Odalarevu, Andhra Pradesh, India

Abstract

High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical and logical operations, the ALU is capable of addition, subtraction, multiplication, AND, OR XOR, and NOT.Xilinx Vivado is used for simulation while Verilog HDL is used for implementation. Time-sensitive applications can benefit from the suggested architecture’s optimisation to reduce critical path latency and increase processing performance. Additionally, the architecture exhibits enhanced scalability and hardware resource utilisation, making it simple to expand to larger bit-width systems. Additionally, the ALU is appropriate for high-performance and low-power VLSI systems due to the incorporation of power efficiency concerns. Modern CPUs, digital signal processing units, and embedded systems may be easily integrated with the design because to its modular nature. It is appropriate for high-speed VLSI applications since the results demonstrate lower latency and better performance when compared to traditional ALU designs guaranteeing dependable performance in next technologies.

Keywords: ALU, Vedic Mathematics, Urdhva Tiryagbhyam, Kogge-Stone Adder, Verilog, VLSI

How to cite this article:
Sirigineedi Mounisha, Uppalapati Joshna Venkata Srujana, Vemula Rajesh, Velugubanti Lakshman, Yepuganti Manikanta, I.Rama Satya.Nageswara Rao, Saran Kumar. 64 Bit ALU DESIGN USING VEDIC MATHEMATHICS. International Journal of VLSI Circuit Design & Technology. 2026; 04(01):-.
How to cite this URL:
Sirigineedi Mounisha, Uppalapati Joshna Venkata Srujana, Vemula Rajesh, Velugubanti Lakshman, Yepuganti Manikanta, I.Rama Satya.Nageswara Rao, Saran Kumar. 64 Bit ALU DESIGN USING VEDIC MATHEMATHICS. International Journal of VLSI Circuit Design & Technology. 2026; 04(01):-. Available from: https://journals.stmjournals.com/ijvcdt/article=2026/view=242953


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Ahead of Print Subscription Review Article
Volume 04
01
Received 30/03/2026
Accepted 03/04/2026
Published 05/05/2026
Publication Time 36 Days
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