- Associate Professor, Sree Venkateswara College of Engineering, North Rajupalem, SPSR, Nellore, Andhra Pradesh, India
- B. Vijayalakshmi, Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, Andhra Pradesh, India
Abstract
This paper introduces a novel and enhanced Gabor filter design aimed at addressing the demands of image processing applications using the Verilog Hardware Description Language (HDL). Specifically, it leverages the Reconstruct Gabor filter technique to elevate the performance and quality of standard image outputs. The primary objective of this research endeavor is to simplify the study, conduct an in-depth analysis, and substantially enhance the design’s efficiency, all while ensuring the preservation of its core functionality. The proposed approach takes a comprehensive approach to address issues related to sizing complexities and to refine the coding style, making it more amenable for synthesis. An innovative feature of this method revolves around the replacement of the incumbent Multiplication Accumulation Unit (MAC) with a more optimized MAC unit. In the realm of digital signal processing, the multiply-accumulate operation takes on pivotal significance, as it encompasses the crucial task of computing the product of two numbers and the subsequent accumulation of the result within an accumulator, contributing to an overall enhancement in processing capabilities and computational efficiency.
Keywords: Gabor filter, image processing, MAC unit, sizing compilation, memory optimization, control unit, Xilinx, and Verilog HDL
[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]
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References
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| Volume | 01 |
| Issue | 02 |
| Received | November 21, 2023 |
| Accepted | January 2, 2024 |
| Published | February 12, 2024 |