Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation

Year : | Volume : 01 | Issue : 02 | Page : –
By

    Malyadri Paduchur

  1. Associate Professor, Sree Venkateswara College of Engineering, North Rajupalem, SPSR, Nellore, Andhra Pradesh, India
  2. B. Vijayalakshmi, Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, Andhra Pradesh, India

Abstract

This paper introduces a novel and enhanced Gabor filter design aimed at addressing the demands of image processing applications using the Verilog Hardware Description Language (HDL). Specifically, it leverages the Reconstruct Gabor filter technique to elevate the performance and quality of standard image outputs. The primary objective of this research endeavor is to simplify the study, conduct an in-depth analysis, and substantially enhance the design’s efficiency, all while ensuring the preservation of its core functionality. The proposed approach takes a comprehensive approach to address issues related to sizing complexities and to refine the coding style, making it more amenable for synthesis. An innovative feature of this method revolves around the replacement of the incumbent Multiplication Accumulation Unit (MAC) with a more optimized MAC unit. In the realm of digital signal processing, the multiply-accumulate operation takes on pivotal significance, as it encompasses the crucial task of computing the product of two numbers and the subsequent accumulation of the result within an accumulator, contributing to an overall enhancement in processing capabilities and computational efficiency.

Keywords: Gabor filter, image processing, MAC unit, sizing compilation, memory optimization, control unit, Xilinx, and Verilog HDL

[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]

How to cite this article: Malyadri Paduchur, [email protected] Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation ijvcdt ; 01:-
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References

  1. Idros, M.F.M., Mohamed, S.A., Razak, A.H.A., Zoolfakar, A.S.A., Al-Junid, S.A.M. (Year). Improvisation of Gabor filter design using Verilog HDL. 2010 International Conference on Electronic Devices, Systems and Applications. 11-14 April 2010; Kuala Lumpur, Malaysia. US: IEEE Press; 2023
  2. Vasily, K.S., Moshnyaga, G., Tamaru, K. (Year). A memory-based architecture for real-time convolution with variable kernels. ISCAS ’98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187). 31 May 1998- 03 June 1998; Monterey, CA, USA. US: IEEE Press.
  3. Razak, A.H.A., Taharim, R.H. (Year). Implementing Gabor Filter for Fingerprint Recognition using Verilog HDL. 2009 5th International Colloquium on Signal Processing & Its Applications. 06-08 March 2009; Kuala Lumpur, Malaysia. US: IEEE Press; 2009.
  4. Benedetti, A. Prati and N. Scarabottolo, “Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure,” 24th EUROMICRO Conference (Cat. No.98EX204), Vasteras, Sweden, 1998, Pages. 123-130 vol.1, doi: 10.1109/EURMIC.1998.711786.
  5. Y. H. Cheung, P. H. W. Leong, E. K. C. Tsang, and B. E. Shi, “Implementation of Gabor-type filters on field programmable gate arrays,” Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005., Singapore, 2005, pp. 327-328, doi: 10.1109/FPT.2005.1568584.
  6. Cummings, C.E. (2002). Verilog-2001 Behavioral and Synthesis Enhancements. In: Mignotte, A., Villar, E., Horobin, L. (eds) System on Chip Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6674-5_2
  7. Bhatnagar, H. (Year). Advanced ASIC Chip Synthesis. Kluwer Academic Publisher, Pages. 202-203.
  8. Gayathri, Dr V. Sridhar. Design and simulation of Gabor filter using verilog HDL. International Journal of Latest Trends in Engineering and Technology (IJLTET). Vol. 2 Issue 2 March 2013; Pages-77-83.
  9. Naheean Rahim, Shamayla Islam, and Iqbalur R. Rokon. Design of a Modified Gabor Filter with Vedic Multipliers Using Verilog HDL. International Journal of Information and Electronics Engineering, Vol. 5, Issue No. 5, September 2015. Pages-361-365.

Regular Issue Subscription Original Research
Volume 01
Issue 02
Received November 21, 2023
Accepted January 2, 2024
Published