Kalvala Shylaja
M. Satya Narayana
- Student, Holy Mary Institute of Technology and Science, Hyderabad, India
- Professor, Holy Mary Institute of Technology and Science, Hyderabad, India
Abstract
In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system’s performance. An improved design can lower power consumption, and delay, and maintain good performance in the full adder circuit even at low supply voltages. Furthermore, giving complete adders enough driving power is critical even under varying loading circumstances, preventing errors, and generating balanced outputs is critical. The proposed hybrid full adder has low power and energy consumption compared to other full adder designs. Finally, a four-operand, eight-bit carry-save adder the final carry propagate adder was implemented using the proposed full adder, and its performance is analyzed based on its average power consumption in 16nm technology. This design also Wave rage power consumption compared to CSA implementation using other existing full adder design styles
Keywords: Full adder, CSA, compressors, comparators, parity checkers
[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]
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References
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| Volume | 01 |
| Issue | 02 |
| Received | November 3, 2023 |
| Accepted | November 8, 2023 |
| Published | January 10, 2024 |