Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.

Year : 2024 | Volume : 01 | Issue : 02 | Page : 17-28
By

    Kalvala Shylaja

  1. M. Satya Narayana

  1. Student, Holy Mary Institute of Technology and Science, Hyderabad, India
  2. Professor, Holy Mary Institute of Technology and Science, Hyderabad, India

Abstract

In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system’s performance. An improved design can lower power consumption, and delay, and maintain good performance in the full adder circuit even at low supply voltages. Furthermore, giving complete adders enough driving power is critical even under varying loading circumstances, preventing errors, and generating balanced outputs is critical. The proposed hybrid full adder has low power and energy consumption compared to other full adder designs. Finally, a four-operand, eight-bit carry-save adder the final carry propagate adder was implemented using the proposed full adder, and its performance is analyzed based on its average power consumption in 16nm technology. This design also Wave rage power consumption compared to CSA implementation using other existing full adder design styles

Keywords: Full adder, CSA, compressors, comparators, parity checkers

[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]

How to cite this article: Kalvala Shylaja, M. Satya Narayana Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology. ijvcdt 2024; 01:17-28
How to cite this URL: Kalvala Shylaja, M. Satya Narayana Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology. ijvcdt 2024 {cited 2024 Jan 10};01:17-28. Available from: https://journals.stmjournals.com/ijvcdt/article=2024/view=130986

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References

Goel, A. Kumar, and M. A. Bayoumi, “Design of robust, energy efficient full adders for deep-sub micrometer design using hybrid- CMOS logic style,” IEEE Trans. Very Large Scale Integr. Syst., vol. 14, Issue no. 12, pages.1309– 1321, Dec.2006, IEEE Xplore.
Aguirre-Hernandez and M. Linares-Aranda, “CMOS Full-Adders for Energy- Efficient Arithmetic Applications,” IEEE Trans. Very Large Scale Integr. Syst., vol.19, no.4, pages.718–721, April 2011, IEEE Xplore.
K. and R. K. Sharma, “An Energy Efficient Logic Approach to Implement CMOS full adder,” J Circuit Syst. Comp, vol.26, Issue no. 5, pages.1–20, May 2017, World Scientific. https://www.worldscientific.com/doi/abs/10.1142/S0218126617500840
Amini-Valashani, M. Ayat, and S. Mirzakuchaki, “Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder,” Microelectronics J., vol. 74, January, pp.49–59,2018, Elsevier. https://www.sciencedirect.com/science/article/abs/pii/S0026269217305360
Shoba and R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Eng. Sci. Technol. an Int. J., vol. 19, Issue no. 1, pages. 485–496, 2016, Elsevier. https://www.sciencedirect.com/science/article/pii/S2215098615001512
A. Kamsani, V. Thangasamy, S.J. Hashim, Z. Yusoff, M.F. Bukhori, and K. N. Hamidon, “A low power multiplexer-based pass transistor logic full adder”, in RSM – IEEE Regional Symposium on Micro and Nano Electronics, Proceedings, Aug.2015, IEEE Xplore. https://ieeexplore.ieee.org/document/7354994/authors#authors
Bhattacharyya, S. Member, B. Kundu, S. Ghosh, and V. Kumar, “Performance Analysis of a Low-Power High-Speed Hybrid1-bit Full Adder Circuit,” IEEE Trans. Very Large Scale Integr. Syst., vol. 23, Issue no.10, pages.1–8, Oct. 2015, IEEE Xplore. https://ieeexplore.ieee.org/document/6912977
Goel, A. Kumar and M. A. Bayoumi, “Design of robust energy-efficient full adders for deep-sub micrometer design using hybrid-CMOS logic style”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, Issue no. 12, pages. 1309-1321, Dec. 2006, IEEE Xplore.
Shalem, L. K. John, and E. John, “A novel low power energy recovery full adder cell”, Proc. Great Lake Symp. VLSI, pages. 380-380, 1999, IEEE Xplore.
Nan and W. Haomin, “A new design of the CMOS full adder”, IEEE J. Solid-State Circuits, vol. 27, Issue no. 5, pages. 840-844, 1992, IEEE Xplore.


Regular Issue Subscription Original Research
Volume 01
Issue 02
Received November 3, 2023
Accepted November 8, 2023
Published January 10, 2024