Implementation of Adders Using Ternary Based Multiple Valued Logic

Year : 2023 | Volume :01 | Issue : 02 | Page : 1-8
By

    M. Mani Kumari

  1. K. Aishwarya

  2. B. Sukruthi

  1. Assistant Professor, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, India
  2. Student, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, India
  3. Student, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, India

Abstract

In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential opportunities for the improvement of present VLSI circuit designs. Multi value logic can carry more information on single line. The key benefits of MVL are Increased data density, delay, reduced dynamic power dissipation and chip area. The major area of binary logic ICs are occupied by interconnections. The more effective utilization of interconnections is possible which uses a larger set of signals over the small area in MVL devices. The higher radix in use is the ternary (radix – 3) and Quaternary (radix – 4). In this paper our objective is to implement different high speed low power adders like RCA and CLA by using ternary based multiple valued logic. The functional verification is performed by using Xilinx ISE design suite by considering Verilog HDL.

Keywords: Ternary, MVL, CSKA, CSLA, RCA, HDL

[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]

How to cite this article: M. Mani Kumari, K. Aishwarya, B. Sukruthi.Implementation of Adders Using Ternary Based Multiple Valued Logic.International Journal of VLSI Circuit Design & Technology.2023; 01(02):1-8.
How to cite this URL: M. Mani Kumari, K. Aishwarya, B. Sukruthi , Implementation of Adders Using Ternary Based Multiple Valued Logic ijvcdt 2023 {cited 2023 Dec 04};01:1-8. Available from: https://journals.stmjournals.com/ijvcdt/article=2023/view=128946


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Regular Issue Subscription Original Research
Volume 01
Issue 02
Received September 27, 2023
Accepted October 10, 2023
Published December 4, 2023
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