Journal of VLSI Design Tools & Technology

Journal of VLSI Design Tools and Technology Cover

Journal of VLSI Design Tools and Technology

ISSN: 2249-474X

Editor Overview

JOVDTT maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

Dr. Brajesh Kumar Kaushik

Dr. Brajesh Kumar Kaushik

Professor Indian Institute of Technology, Roorkee Editor in Chief Journal of VLSI Design Tools and Technology
Email : Institutional Profile Link : http://ece. . .

Publisher

STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd.
A-118, 1st Floor, Sector-63, Noida, U.P. India, Pin – 201301

E-mail: [email protected]
(Tel): (+91) 0120- 4781 200
(Mob) (+91) 9810078958, +919667725932

About Journal

Journal of VLSI Design Tools and Technology (JOVDTT): 2249-474X(e) is a peer-reviewed hybrid open-access journal launched in 2015

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Journals Particular

Title
Journal of VLSI Design Tools & Technology
Journal Abbreviation
JOVDTT
Issues Per Year
(Frequency)
3 Issues (Jan-April,May-August,Sept-Dec)
ISSN
2249-474X
Impact Factor(SJIF)
Publisher
STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd.
DOI
Copyright
STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd.
Starting Year
2011
Subject
Electrical Engineering
Language
English
Publication Format
Hybrid Open Access
Type of Publication
Peer-reviewed Journal (Refereed Journal)
Website
https://journals.stmjournals.com/journal/JOVDTT
Address
A-118, 1st Floor, Sector-63, Noida, U.P. India, Pin – 201301
Principal Contact

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Latest Article
Vol-14 Issue-01 2024
Regular Issue  Subscription Review Article Published on :- May 25, 2024
Exploring the Dynamics of Memristors: Mechanisms, Models, and Multifaceted Applications
Dharmendra Ganage, Heramb Bedke, Prasad Rajendra Kulkarni, Shreyangi Edake
Keywords: Memristor, Memristor Emulator, Neuromorphic computing, Nano-Scaling.

Regular Issue  Subscription Original Research Published on :- May 28, 2024
Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Kuldeep Jaiswal, Sunil Kumar Shah
Keywords: FPGA, DDR, DRAM, High-Speed Interfacing, Pipelining, Area Optimization, Verilog HDL, Xilinx EDA, Integrated Software Environment (ISE).

Regular Issue  Subscription Review Article Published on :- May 24, 2024
Hardware Synchronization for Embedded Multi-core Processors
Tejasvini Bansode, Anjali Pise
Keywords: PowerPC processor, FPGA, digital signal processing, SNR, RPR, VOS, VLSI systems,

Regular Issue  Subscription Review Article Published on :- June 4, 2024
Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Pallavi Prakash Mete, Omprakash Rajankar
Keywords: Three operand adder, carry save adder, Han-Carlson adder, Modular arithmetic,Kogge stone parallel prefix

Regular Issue  Subscription Original Research Published on :- May 30, 2024
High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Banoth Krishna, Sandeep Singh Gill, Amod Kumar
Keywords: High speed comparator, Latch comparator, Double tail comparator, High speed ADC

JOVDTT
Open Access
Topic

VLSI, Static CMOS, Dynamic CMOS, Domino logic, MOSFET, Simulation

Abstract Submission deadline : 30-Nov-2024 Mansusript Submission deadline : 25-Dec-2024
Open Access
Topic

Arithmetic Functions, Fast Fourier Transform, Round Robin Arbiter

Abstract Submission deadline : 30-Nov-2024 Mansusript Submission deadline : 25-Dec-2024
Open Access
Topic

Abstract Submission deadline : 30-Nov-2024 Mansusript Submission deadline : 25-Dec-2024
Open Access
Topic

Process stages, Lexical processing, Algorithm optimization, Control/Dataflow analysis, Library

Abstract Submission deadline : 30-Nov-2024 Mansusript Submission deadline : 25-Dec-2024