Subscribed Libraries
Management ePaper
Total: 5217
| Sn | Title | Abstract | Full Text |
|---|---|---|---|
| 1 | Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing | Abstract | Full Text |
| 2 | Decimator Design for Sigma-Delta ADC | Abstract | Full Text |
| 3 | An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based Amplifier for Analog Signal-based Applications | Abstract | Full Text |
| 4 | An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator | Abstract | Full Text |
| 5 | Power Estimation for VLSI Circuits Using Neural Networks | Abstract | Full Text |
| 6 | Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect | Abstract | Full Text |
| 7 | Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors | Abstract | Full Text |
| 8 | Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime | Abstract | Full Text |
| 9 | An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input | Abstract | Full Text |
| 10 | Implementation and Simulation of MOSFET Switch for Switched Capacitor Circuits | Abstract | Full Text |
| 11 | Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology | Abstract | Full Text |
| 12 | Design and Implementation of Low Noise Amplifier using 90 nm MOS Technology for Bluetooth | Abstract | Full Text |
| 13 | A Low Power Variable Gain Amplifier for Biomedical Application | Abstract | Full Text |
| 14 | Nonlinear Semiconductor Device Modeling using Neural Networks | Abstract | Full Text |
| 15 | Comparative Analysis of Low-Power Adiabatic Techniques | Abstract | Full Text |
| 16 | Design of High-Speed TIQ Comparator for Flash-Type ADC for (WPMOS/LPMOS) > 1 | Abstract | Full Text |
| 17 | A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture | Abstract | Full Text |
| 18 | Methodology of Standard Cell Library Design in .LIB Format | Abstract | Full Text |
| 19 | Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers | Abstract | Full Text |
| 20 | A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits | Abstract | Full Text |
| 21 | A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit | Abstract | Full Text |
| 22 | Triangular Waveform Generation using Mixed Signal Modeling | Abstract | Full Text |
| 23 | A Cuckoo Search based Approach for Solving Standard Cell Placement Problem | Abstract | Full Text |
| 24 | Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder | Abstract | Full Text |
| 25 | Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88ΓÇô108 MHz Wireless System for Multi Standard Receiver | Abstract | Full Text |
| 26 | A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology | Abstract | Full Text |
| 27 | Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes | Abstract | Full Text |
| 28 | Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology | Abstract | Full Text |
| 29 | Design of Grounded Immittance Simulator using Single CDBA | Abstract | Full Text |
| 30 | A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic | Abstract | Full Text |
| 31 | Logic Optimization Algorithm based on ShannonΓÇÖs Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation | Abstract | Full Text |
| 32 | Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter | Abstract | Full Text |
| 33 | Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder | Abstract | Full Text |
| 34 | Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression | Abstract | Full Text |
| 35 | Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor | Abstract | Full Text |
| 36 | Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects | Abstract | Full Text |
| 37 | A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFETΓÇÖs Threshold Voltage Extractor | Abstract | Full Text |
| 38 | A New High Speed Low Power 1 Bit Full Adder | Abstract | Full Text |
| 39 | A High Performance Reference Circuit with Optimized Input Offset Operational Amplifier using Device Mismatch Model | Abstract | Full Text |
| 40 | Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology | Abstract | Full Text |
| 41 | Performance Analysis of DNA Sequencing Using Smith-Waterman Algorithm on FPGA | Abstract | Full Text |
| 42 | Design of Energy Efficient Clock System | Abstract | Full Text |
| 43 | Reusable FM0/Manchester Encoding Using QCA | Abstract | Full Text |
| 44 | Near Field Wireless Powering of Implantable Devices | Abstract | Full Text |
| 45 | Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits | Abstract | Full Text |
| 46 | Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications | Abstract | Full Text |
| 47 | Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode | Abstract | Full Text |
| 48 | Design and Implementation of an Efficient Ternary Control Unit | Abstract | Full Text |
| 49 | Memristor Modelling for Common Source Amplifier Using 180 nm Technology | Abstract | Full Text |
| 50 | Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology | Abstract | Full Text |
| 51 | CMOS Gm-C IF Filter using SCA for Dual Band Receiver | Abstract | Full Text |
| 52 | All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey | Abstract | Full Text |
| 53 | A Review on Charge Pump Circuits for PLL Applications | Abstract | Full Text |
| 54 | Implementation and Analysis of 32-bit pipelined RISC Processor Architecture | Abstract | Full Text |
| 55 | Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology | Abstract | Full Text |
| 56 | Design of 8 Bit High Speed Pipelined ADC | Abstract | Full Text |
| 57 | Characterization of High Performance Third Generation Current Conveyor using CMOS Technology | Abstract | Full Text |
| 58 | Automated Access Backdoor for UVM_REG Layer | Abstract | Full Text |
| 59 | Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave | Abstract | Full Text |
| 60 | Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style | Abstract | Full Text |
| 61 | Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating | Abstract | Full Text |
| 62 | A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier | Abstract | Full Text |
| 63 | 4-Bit Magnitude Comparator Design using Different Logic Styles | Abstract | Full Text |
| 64 | Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter | Abstract | Full Text |
| 65 | Comparative Analysis of High Speed Comparator for A to D Converters | Abstract | Full Text |
| 66 | Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology | Abstract | Full Text |
| 67 | Characterization of High Speed Phase Frequency Detector Circuit | Abstract | Full Text |
| 68 | Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications? | Abstract | Full Text |
| 69 | Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System | Abstract | Full Text |
| 70 | Optimized AES Implementation on Leon3 | Abstract | Full Text |
| 71 | Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique | Abstract | Full Text |
| 72 | Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology | Abstract | Full Text |
| 73 | Designing of GaAs Based Resonant Tunneling Diode and Nano Scale Applications with Considering NEGF | Abstract | Full Text |
| 74 | A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions | Abstract | Full Text |
| 75 | A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network | Abstract | Full Text |
| 76 | Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier | Abstract | Full Text |
| 77 | Performance Analysis of CMOS and FinFET Based SRAM | Abstract | Full Text |
| 78 | Design, Verification and Circuit Level Implementation of a Ballistic MOSFET | Abstract | Full Text |
| 79 | An Area Delay Optimized Carry-Select Adder | Abstract | Full Text |
| 80 | Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter | Abstract | Full Text |
| 81 | A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault | Abstract | Full Text |
| 82 | Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits | Abstract | Full Text |
| 83 | A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing | Abstract | Full Text |
| 84 | Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime | Abstract | Full Text |
| 85 | A Review on FPGA Parallel Architecture for Object Detection | Abstract | Full Text |
| 86 | Comparative Analysis of Different SRAM Cells Architecture at 70 nm | Abstract | Full Text |
| 87 | Characterization of Low Power-Low Jitter Digital PLL | Abstract | Full Text |
| 88 | Design of Three-Stage Pipelined Floating Point Arithmetic Operators | Abstract | Full Text |
| 89 | High Gain Antenna Array (2×1 and 4×1) Design for WLAN Application | Abstract | Full Text |
| 90 | Review Paper To Design a Low Power CNTFET Based XOR Gate | Abstract | Full Text |
| 91 | Review Paper: Low Power SRAM Cell using FinFET Technology | Abstract | Full Text |
| 92 | High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology | Abstract | Full Text |
| 93 | Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques | Abstract | Full Text |
| 94 | AXI Bridge and DMA/Bridge Subsystem for PCIe | Abstract | Full Text |
| 95 | Memristor based Material Implication Logic for Implementation of Basic logic Gates and Circuits | Abstract | Full Text |
| 96 | High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator | Abstract | Full Text |
| 97 | Fault Detection Attainment for Embedded Cores based on Software Test Routines | Abstract | Full Text |
| 98 | Single Bit Low-Power High-Speed Full Adder | Abstract | Full Text |
| 99 | Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node | Abstract | Full Text |
| 100 | High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography | Abstract | Full Text |
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