Subscribed Libraries
Management ePaper
Total: 5217
| Sn | Title | Abstract | Full Text |
|---|---|---|---|
| 1 | Hybrid Intelligent Controllers for Highly Accurate Trajectory Tracking of Manipulator | Abstract | Full Text |
| 2 | Solution of Optimal Reactive Power Dispatch Problem Using a Novel Meta-heuristic Technique | Abstract | Full Text |
| 3 | Efficient Trash Supervision Using Internet of Things | Abstract | Full Text |
| 4 | Transient Analysis of Non-Uniform Windings or Lines with Non-Linear Termination | Abstract | Full Text |
| 5 | Appliance Scheduling Optimization for Demand Response: A Review | Abstract | Full Text |
| 6 | A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic | Abstract | Full Text |
| 7 | Methodical Strategy for STATCOMs Optimal Placement to Enhance Voltage Stability Margin Considering Circular Optimization Algorithm | Abstract | Full Text |
| 8 | Impact of Work Function Variations on Data Stability of FinFET based 6T SRAM Cell | Abstract | Full Text |
| 9 | Recent Developments in MEMS Speaker Technology | Abstract | Full Text |
| 10 | Leveraging cross-coupled domino logic for low-power, two-port SRAM with resilience to Differential Power Analysis (DPA) attacks | Abstract | Full Text |
| 11 | Hardware Implementation of Discrete /Inverse Discrete Cosine Transform Using Redundant Number System CORDIC Processors | Abstract | Full Text |
| 12 | Modelling and Simulation of MPPT Boost Converter in MATLAB | Abstract | Full Text |
| 13 | Quantum Behavior of Charge Carriers in a Symmetrical Double Gate MOSFET | Abstract | Full Text |
| 14 | Hierarchical Methodology Approach to SOC Design: A Comprehensive Look | Abstract | Full Text |
| 15 | Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization | Abstract | Full Text |
| 16 | Wire Network Survivability for Upgraded Consistency in Smart Power Grids | Abstract | Full Text |
| 17 | A Review on Mechanization of Process Planning for Automated Fiber Placement | Abstract | Full Text |
| 18 | The Study on Energy-Efficient Context-Aware Architecture for Wired or Wireless Communication System | Abstract | Full Text |
| 19 | Modelling of DC-DC Adapter use Intent of Photovoltaic Module Coordinating with Load | Abstract | Full Text |
| 20 | Investigations on the impact of modulation formats and weather conditions in FSO link employing polarization division multiplexing and coherent detection-orthogonal frequency division multiplexing | Abstract | Full Text |
| 21 | Adaptive Hysteresis Band Current Controller for the Shunt Active Power Filter Using the d-q0 Reference Frame Theory | Abstract | Full Text |
| 22 | Simulation and Analysis of Grid Integrated Solar PV System under Variable Climatic Conditions | Abstract | Full Text |
| 23 | Implementation of 32 bit parallel adder using XILINX IPCORES A Case Study | Abstract | Full Text |
| 24 | Switching Loss Calculation of Power MOSFET using the Estimation Technique | Abstract | Full Text |
| 25 | Artificial Intelligence Techniques in Switchgear and Protection | Abstract | Full Text |
| 26 | Simulation of Three Section Multilevel Inverter with Reduced Range of Switches | Abstract | Full Text |
| 27 | Privacy Preserving Cloud Data Access using Control and Automation Technique | Abstract | Full Text |
| 28 | An Overview of the Contemporary GSM system in Digital world | Abstract | Full Text |
| 29 | Maximum Power Point Tracker and its model in MATLAB | Abstract | Full Text |
| 30 | Organic Material Based Device of VLSI :Solar Cell | Abstract | Full Text |
| 31 | An Overview to Transmitter Device Or Gesture Device Components | Abstract | Full Text |
| 32 | An Outline of Receiver Device Or Gesture Device Components | Abstract | Full Text |
| 33 | A Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB | Abstract | Full Text |
| 34 | Optimal Size and Location of Capacitor Bank for Reactive Power Compensation Using Genetic Algorithm | Abstract | Full Text |
| 35 | The Efficiency of Solar Panel: Case Study of Cross River State University of Technology, Nigeria | Abstract | Full Text |
| 36 | Performance Estimation of VLSI Design | Abstract | Full Text |
| 37 | A New Current Mode Quadrature Oscillator using Current Differencing Transconductance Amplifier (CDTA) | Abstract | Full Text |
| 38 | Design of CMOS AM Modem for Wireless Sensors | Abstract | Full Text |
| 39 | Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 ┬╡m Technology | Abstract | Full Text |
| 40 | Gain Controlled Sinusoidal Oscillator Using Current Controlled Current Conveyors | Abstract | Full Text |
| 41 | Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA | Abstract | Full Text |
| 42 | Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability | Abstract | Full Text |
| 43 | High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography | Abstract | Full Text |
| 44 | Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node | Abstract | Full Text |
| 45 | Single Bit Low-Power High-Speed Full Adder | Abstract | Full Text |
| 46 | Implementation of RSA and CRT-RSA with MIST to Resist Power Analysis Attacks | Abstract | Full Text |
| 47 | Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology | Abstract | Full Text |
| 48 | Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology | Abstract | Full Text |
| 49 | Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device | Abstract | Full Text |
| 50 | Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops | Abstract | Full Text |
| 51 | Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture | Abstract | Full Text |
| 52 | Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology | Abstract | Full Text |
| 53 | A Novel Approach Based On-Chip High Speed Optical Interconnection Network | Abstract | Full Text |
| 54 | Implementation of Carry Select Adder with Reduced Area Scheme | Abstract | Full Text |
| 55 | A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure | Abstract | Full Text |
| 56 | Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers | Abstract | Full Text |
| 57 | Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform | Abstract | Full Text |
| 58 | Design of High-Speed and Low-Power Carry Skip Adder | Abstract | Full Text |
| 59 | A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique | Abstract | Full Text |
| 60 | Survey of System-on-Chip Modular Test Approach | Abstract | Full Text |
| 61 | Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications | Abstract | Full Text |
| 62 | VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter | Abstract | Full Text |
| 63 | Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy | Abstract | Full Text |
| 64 | Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier | Abstract | Full Text |
| 65 | Design of FPGA Based ALU Using Reversible Logic Gates | Abstract | Full Text |
| 66 | Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog | Abstract | Full Text |
| 67 | Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC | Abstract | Full Text |
| 68 | Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power | Abstract | Full Text |
| 69 | A New TGC-Differential Input Stage to Modify Dynamic Comparator | Abstract | Full Text |
| 70 | Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM | Abstract | Full Text |
| 71 | Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique | Abstract | Full Text |
| 72 | Design and RTL Implementation for AHB-APB Bridge on SoC | Abstract | Full Text |
| 73 | Design and Implementation of Low Power 8-bit Level Crossing ADC | Abstract | Full Text |
| 74 | Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review | Abstract | Full Text |
| 75 | Challenges Beyond 100 nm MOS Devices | Abstract | Full Text |
| 76 | Layout Design, Fabrication and Characterization of n-Channel MOSFET | Abstract | Full Text |
| 77 | Design and Performance Trends of Low Power Sigma-Delta A/D Converters | Abstract | Full Text |
| 78 | A Differentiator Based on Second Generation Current Controlled Conveyor | Abstract | Full Text |
| 79 | GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology | Abstract | Full Text |
| 80 | Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell | Abstract | Full Text |
| 81 | Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology | Abstract | Full Text |
| 82 | Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation | Abstract | Full Text |
| 83 | Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence | Abstract | Full Text |
| 84 | Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell | Abstract | Full Text |
| 85 | Switched Capacitor-based RC Filter | Abstract | Full Text |
| 86 | Simulation Study of Tapered Shape FinFET | Abstract | Full Text |
| 87 | A Review for Power Optimization in MOS Devices using Different Logic Styles | Abstract | Full Text |
| 88 | Hardware Implementation of Configurable Multi Image Fusion | Abstract | Full Text |
| 89 | A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit | Abstract | Full Text |
| 90 | Technology Limits on Differential Gain and Unity-gain Bandwidth of a Differential Amplifier: A Theoretical Analysis | Abstract | Full Text |
| 91 | System Level Modeling of ISMB Quadrature Transceiver | Abstract | Full Text |
| 92 | Power Reduction at 90 nm through Circuit Level Modification | Abstract | Full Text |
| 93 | Performance Analysis of Fe/SiO2/Fe MTJ and Ni/Al2O3/Ni MTJ-based Magnetoresistive Random Access Memories (MRAMs) | Abstract | Full Text |
| 94 | Low-Voltage Low-Power Single Supply Rail-to-Rail High Resolution Comparator in 0.18 ┬╡m CMOS Technology | Abstract | Full Text |
| 95 | Low Power RF QPSK MODEM Design | Abstract | Full Text |
| 96 | High-speed CMOS ADCs Design | Abstract | Full Text |
| 97 | Detailed Study of Working and Applications of FinFET Technology and Its Adaptability in Current Era | Abstract | Full Text |
| 98 | Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System | Abstract | Full Text |
| 99 | Design of 16-bit Pipelined RISC Processor | Abstract | Full Text |
| 100 | Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing | Abstract | Full Text |
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