JOVDTT 2024
Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Design and Implementation of Low Latency 16-bit Full Adder
Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips
RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools
Vehicle Black Box Systems: Evolution, Implementation, and Impact on Road Safety
Surveillance Car using ESP32 Cam Module by using GAN Model
Performance and Reliability Analysis of NAND Flash Memory through Characterization
Optimizing Routing and Placement of VLSI Circuits with Differential Algorithms and Neural Networks
Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed
High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Hardware Synchronization for Embedded Multi-core Processors
Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Exploring the Dynamics of Memristors: Mechanisms, Models, and Multifaceted Applications