Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed

Year : 2024 | Volume : 14 | Issue : 02 | Page : 1 13
    By

    Ayushi Vinodia,

  • Kanchan Cecil,

  1. Student,, Jabalpur Engineering College,, Madhya Pradesh,, India
  2. Professor,, Jabalpur Engineering College,, Madhya Pradesh,, India

Abstract

This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces read and write delays, outperforming traditional 6T, RHRD-12T, SEUH-12T, and NHRC-14T SRAM cells. Specifically, the HS-14T demonstrates an impressive 80% reduction in read delay compared to NHRC-14T, an 88% reduction compared to RHRD-12T, and an 89% reduction compared to SEUH-14. In terms of write delay, the HS-14T shows a 66% reduction compared to NHRC-14T, a 98.75% reduction compared to RHRD-12T, and a 25% reduction compared to SEUH-14. Additionally, the HS-14T exhibits an 18% decrease in leakage current compared to RHRD-12T and a 1.63% decrease compared to SUEH-12T, though it shows a 55% increase compared to NHRC-14T. The software used for simulations is Symica DE, and the technology node is 45 nm. This study highlights the HS-14T SRAM’s potential for significantly enhanced performance and productivity in various computing systems, making it a compelling choice for applications where rapid data access and energy efficiency are paramount.

Keywords: SRAM cell, read delay, write delay leakage current, Symica DE, minicomputers, cache memory

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Ayushi Vinodia, Kanchan Cecil. Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed. Journal of VLSI Design Tools and Technology. 2024; 14(02):1-13.
How to cite this URL:
Ayushi Vinodia, Kanchan Cecil. Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed. Journal of VLSI Design Tools and Technology. 2024; 14(02):1-13. Available from: https://journals.stmjournals.com/jovdtt/article=2024/view=161553


References

  1. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, “A read-static-noise-margin-free sram cell for low-vdd and high-speed applications,” IEEE journal of solid-state circuits, vol. 41, no. 1, pp. 113–121, 2005.
  2. Pal and A. Islam, “Variation tolerant differential 8t sram cell for ultralow power applications,” IEEE transactions on computer-aided design of integrated circuits and systems, vol. 35, no. 4, pp. 549 558, 2015.
  3. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi, S. Richter, Q.-T. Zhao, and S. Mantl, “Impact of tfet unidirectionality and ambipolarity on the performance of 6t sram cells,” IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 223–232, 2015.
  4. Pal and A. Islam, “9-t sram cell for reliable ultralow-power ap plications and solving multibit soft-error issue,” IEEE Transactions on Device and Materials Reliability, vol. 16, no. 2, pp. 172–182, 2016.
  5. Kushwah and S. K. Vishvakarma, “A single-ended with dynamic feedback control 8t subthreshold sram cell,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 373–377, 2015.
  6. W. Oh, H. Jeong, J. Park, and S.-O. Jung, “Pre-charged local bit line sharing sram architecture for near-threshold operation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 10, pp. 2737–2747, 2017.
  7. Pasandi, R. Mehta, M. Pedram, and S. Nazarian, “Hybrid cell assignment and sizing for power, area, delay-product optimization of sram arrays,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 2047–2051, 2019.
  8. Yang, J. Park, S. C. Song, J. Wang, G. Yeap, and S.-O. Jung, “Single-ended 9t sram cell for near-threshold voltage operation with enhanced read performance in 22-nm finfet technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2748–2752, 2014.
  9. Singh, M. K. Jain, and S. Wairya, “Novel lossless grounded and floating inductance simulators employing a grounded capacitor based on cc-cfa,” Journal of Circuits, Systems and Computers, vol. 28, no. 06, p. 1950093, 2019.
  10. K. Misra, B. Sen, and S. Wairya, “Novel conservative reversible error control circuits based on molecular qca,” International Journal of Computer Applications in Technology, vol. 56, no. 1, pp. 1–17, 2017.
  11. P. Kulkarni, K. Kim, and K. Roy, “A 160 mv robust schmitt trigger based subthreshold sram,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2303–2313, 2007.
  12. Lin, Y.-B. Kim, and F. Lombardi, “A 32nm sram design for low power and high stability,” in 2008 51st Midwest Symposium on Circuits and Systems. IEEE, 2008, pp. 422–425.
  13. Agarwal and K. Roy, “A noise tolerant cache design to re duce gate and sub-threshold leakage in the nanometer regime,” in Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED’03. IEEE, 2003, pp. 18 21.
  14. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “Sram design on 65-nm cmos technology with dynamic sleep transistor for leakage reduction,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 895–901, 2005.
  15. Morifuji, D. Patil, M. Horowitz, and Y. Nishi, “Power optimization for sram and its scaling,” IEEE Transactions on Electron Devices, vol. 54, no. 4, pp. 715–722, 2007.
  16. Athe and S. Dasgupta, “A comparative study of 6t, 8t and 9t decanano sram cell,” in 2009 IEEE Symposium on Industrial Electronics & Applications, vol. 2. IEEE, 2009, pp. 889–894.
  17. Liu and V. Kursun, “Characterization of a novel nine-transistor sram cell,” IEEE transactions on very large scale integration (VLSI) systems, vol. 16, no. 4, pp. 488–492, 2008.
  18. Giterman, M. Vicentowski, I. Levi, Y. Weizman, O. Keren, and A. Fish, “Leakage power attack-resilient symmetrical 8t sram cell,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2180–2184, 2018.
  19. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, and M. Alioto, “Sram for error-tolerant applications with dynamic energy-quality management in 28 nm cmos,” IEEE Journal of Solid state circuits, vol. 50, no. 5, pp. 1310–1323, 2015.
  20. Peng, J. Huang, C. Liu, Q. Zhao, S. Xiao, X. Wu, Z. Lin, J. Chen, X. Zeng, Radiation-hardened 14t SRAM bitcell with speed and power optimized for space application, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27 (2) (2018) 407–415.
  21. Zhao, H. Dong, X. Wang, L. Hao, C. Peng, Z. Lin, X. Wu, Novel radiation-hardened SRAM for immune soft-error in space-radiation environments, Microelectron. Reliab. 140 (2023) 114862.
  22. K. Mukku and R. Lorenzo, “A soft error upset hardened 12T-SRAM cell for space and terrestrial applications,” Memories – Materials, Devices, Circuits and Systems, vol. 6, Dec. 2023, Art. no. 100092.
  23. Pal, D. DivyaSri, W.-H. Ki, and A. Islam, “Radiation-hardened read-decoupled low-power 12T SRAM for space applications,” Int. J. Circ. Theor. Appl., vol. 49, no. 1, pp. 1-14, Jan. 2021. doi: 10.1002/cta.3093.
Regular Issue Subscription Original Research
Volume 14
Issue 02
Received 05/07/2024
Accepted 24/07/2024
Published 07/08/2024
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