Simulation of Adder Circuit Using Reversible Gates in Verilog HDL

Year : 2024 | Volume : 14 | Issue : 03 | Page : 32 38
    By

    Pranav Rao,

  • K. B. Ramesh,

  1. Student, Student, Department of Electronics and Instrumentation Engineering, R.V. College of Engineering, Bengaluru,, Karnataka, India
  2. Associate Professor, Associate Professor, Department of Electronics and Instrumentation Engineering, R.V. College of Engineering, Bengaluru, Karnataka, India

Abstract

The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have achieved a power consumption figure that is 97% lower along with a 15% reduction in junction temperature, as compared to conventional full adder. We have shown the methodology to create and obtain a reversible gate full adder circuit in Xilinx Vivado. Because they rely on irreversible computations, traditional logic gates cause bit erasure and consequent power loss. A developing field called reversible computing promises to solve this issue by guaranteeing that no data is lost during computation, therefore lowering power consumption. In this regard, modeling adder circuits using reversible gates is an important first step towards designing arithmetic circuits that consume less energy. This article uses Verilog Hardware Description Language (HDL), a popular tool for modeling and simulating digital circuits, to examine the design and simulation of a reversible adder circuit.

 

Keywords: Full adder, Verilog HDL, reversible logic, power optimization, Peres gate

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Pranav Rao, K. B. Ramesh. Simulation of Adder Circuit Using Reversible Gates in Verilog HDL. Journal of VLSI Design Tools and Technology. 2024; 14(03):32-38.
How to cite this URL:
Pranav Rao, K. B. Ramesh. Simulation of Adder Circuit Using Reversible Gates in Verilog HDL. Journal of VLSI Design Tools and Technology. 2024; 14(03):32-38. Available from: https://journals.stmjournals.com/jovdtt/article=2024/view=179706


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Regular Issue Subscription Original Research
Volume 14
Issue 03
Received 17/08/2024
Accepted 12/09/2024
Published 24/10/2024
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