Design and Implementation of Low Latency 16-bit Full Adder

Year : 2024 | Volume : 14 | Issue : 03 | Page : 21 31
    By

    Sandeep N. Uttarkar,

  • K. B. Ramesh,

  1. Student, Department of Electronics and Instrumentation Engineering, R.V. College of Engineering (An Autonomous Institution, affiliated to VTU Belagavi), Banglore, Karnataka, India
  2. Associate professor, Department of Electronics and Instrumentation Engineering, R.V. College of Engineering (An Autonomous Institution, affiliated to VTU Belagavi), Banglore, Karnataka, India

Abstract

In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing and systems play a vital role in the analysis and computation of data representation. Electronic systems have gradually become faster and smaller scale. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing processes. The performance of the adder circuit will therefore greatly affect the performance of the CPU. In terms of frequency, general adders like half adders, full adders, ripple-carry adders, carry skip adders, and carry look-ahead adders don’t meet the demands of high-performance processors. To fulfill the required specifications, we suggest in this work a high-frequency 16-bit full-adder architecture. This architecture was simulated using Verilog on the Xilinx ISE 14.7 tool, and it was then built on the field-programmable gate array (FPGA) families.

Keywords: Half adder (HA), full adder (FA), carry-select adder (CSA), carry look-ahead adder (CLA), input-output blocks (IOB), configurable logic blocks (CLB), field-programmable gate array (FPGA)

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Sandeep N. Uttarkar, K. B. Ramesh. Design and Implementation of Low Latency 16-bit Full Adder. Journal of VLSI Design Tools and Technology. 2024; 14(03):21-31.
How to cite this URL:
Sandeep N. Uttarkar, K. B. Ramesh. Design and Implementation of Low Latency 16-bit Full Adder. Journal of VLSI Design Tools and Technology. 2024; 14(03):21-31. Available from: https://journals.stmjournals.com/jovdtt/article=2024/view=176363


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Regular Issue Subscription Original Research
Volume 14
Issue 03
Received 13/08/2024
Accepted 21/08/2024
Published 30/09/2024
380

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