Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic

Year : 2025 | Volume : 15 | Issue : 03 | Page : 21 28
    By

    Deepanshu Joshi,

  • Aman Pal,

  • Dev Vrat Goswami,

  • Kamal Kishor Upadhyay,

  • Shivaji Sinha,

  • Manoj Joshi,

  1. Research Scholar, Department of ECE, JSS Academy of Technical Education Noida, Uttar Pradesh, India
  2. Research Scholar, Department of ECE, JSS Academy of Technical Education Noida, Uttar Pradesh, India
  3. Research Scholar, Department of ECE, JSS Academy of Technical Education Noida, Uttar Pradesh, India
  4. Research Scholar, Department of ECE, JSS Academy of Technical Education Noida, Uttar Pradesh, India
  5. Research Scholar, Department of ECE, JSS Academy of Technical Education Noida, Uttar Pradesh, India
  6. Research Scholar, Department of ECE, JSS Academy of Technical Education Noida, Uttar Pradesh, India

Abstract

Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various prototypical digital systems. In this research work, we employed an awesome configuration using an efficient D flip flop structure – 1 Fredkin Gate and 2 Feynman Gates—alongside 4X1 multiplexer design made of standard Fredkin gates, and we have designed and realized this design really well for an optimized 4 bit reversible universal shift register, or 4 bit RUSR. Using necessary metrics including things like garbage output counts (GO), gate counts (GC) and quantum cost (QC), we’re showing that we’ve got really efficient design. We’ve achieved the minimum quantum cost and we also went with fewer reversible logic gates which increase the efficiency of our design that’s optimized for resources. Validation and simulation of the reversible 4-bit universal shift register circuit were carried out using Xilinx Vivado 2024.2 software.

Keywords: Quantum Cost (QC), Garbage Outputs (GO), Gate Count (GC), Reversible Logic, Universal Shift Register (USR), Fredkin Gate, Feynman Gate, Ancilla Inputs (AI).

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Deepanshu Joshi, Aman Pal, Dev Vrat Goswami, Kamal Kishor Upadhyay, Shivaji Sinha, Manoj Joshi. Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic. Journal of VLSI Design Tools and Technology. 2025; 15(03):21-28.
How to cite this URL:
Deepanshu Joshi, Aman Pal, Dev Vrat Goswami, Kamal Kishor Upadhyay, Shivaji Sinha, Manoj Joshi. Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic. Journal of VLSI Design Tools and Technology. 2025; 15(03):21-28. Available from: https://journals.stmjournals.com/jovdtt/article=2025/view=234185


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Regular Issue Subscription Review Article
Volume 15
Issue 03
Received 05/06/2025
Accepted 31/07/2025
Published 13/12/2025
Publication Time 191 Days
130

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