RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor

Year : 2025 | Volume : 15 | Issue : 03 | Page : 1 10
    By

    Abhishek Patel,

  • Pankaj Verma,

  1. Student, School of VLSI design and Embedded System, National Intitute of technology, Kurukshetra, Haryana, India
  2. Assistant Professor, Department of Electronics and Communication , National Intitute of technology, Kurukshetra, Haryana, India

Abstract

This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages including floorplanning, placement, clock tree synthesis (CTS), routing, and signoff verification. To enhance the design’s power, advanced optimization techniques such as concurrent clock and data optimization[1] (CCDO), clock gating, and self-gating were employed during the physical design phase. These techniques collectively contributed to a substantial improvement in power efficiency and timing closure. Clock network optimization was carefully conducted to reduce skew, latency, and unnecessary dynamic switching activity. The final physical implementation demonstrated a notable total power reduction of approximately 15.9%, while ensuring performance integrity and meeting stringent timing constraints. The outcomes validate the effectiveness of integrating Synopsys Fusion Compiler in achieving a streamlined RTL-to-GDSII flow and highlight its potential for next-generation processor designs in energy-sensitive applications.

Keywords: RTL-to-GDSII, RISC-V processor, Synopsys Fusion Compiler, Power optimization, Clock network design, Clock tree synthesis (CTS), Physical design flow, Low-power design, EDA tools.

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Abhishek Patel, Pankaj Verma. RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor. Journal of VLSI Design Tools and Technology. 2025; 15(03):1-10.
How to cite this URL:
Abhishek Patel, Pankaj Verma. RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor. Journal of VLSI Design Tools and Technology. 2025; 15(03):1-10. Available from: https://journals.stmjournals.com/jovdtt/article=2025/view=234162


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Regular Issue Subscription Original Research
Volume 15
Issue 03
Received 24/05/2025
Accepted 21/06/2025
Published 13/12/2025
Publication Time 203 Days
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