CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.

Year : 2025 | Volume : 15 | Issue : 01 | Page : 8 17
    By

    Abhishek Agwekar,

  • Laxmi Singh,

  1. PhD Scholar, Department of Electronics & Communication Engineering, Rabindranath Tagore University (RNTU), Bhopal, Madhya Pradesh, India
  2. Professor & Head, Department of Electronics & Communication Engineering, Rabindranath Tagore University (RNTU), Bhopal, Madhya Pradesh, India

Abstract

Analog computing techniques are gaining attention for machine learning (ML) applications due to their ability to reduce computational complexity. Continuous operations such as addition and subtraction offer a simpler and more efficient approach compared to probabilistic product decoding, which can be sensitive to noise and inconsistent measurements. This paper presents a simulated VLSI implementation of a broadcast edge connection, independent of the MOS component model, along with experimental results. The implementation requires in-loop circuit training to address device incompatibilities and reduce artifacts. To speed up wafer-in-the-loop training, circuits are reweighted to ensure that simulated functions remain unchanged during training and inference. We propose a simulation paradigm and circuit using “positive” functions that remain invariant to transistor bias and ambient temperature variations. Additionally, we describe a 3-layer neural network based on S-AC (Shape-Based Analog Computing) with six hidden nodes. This design utilizes differential compressive input and in-memory computing to store weights, significantly reducing data movement energy. Experimental results demonstrate that S-AC circuits are tenable, conflict-free, and capable of operating under various biasing conditions and temperatures. The S-AC framework allows a trade-off between computational accuracy, speed, power, and area. This architecture is ideal for high-speed ML training in the SI regime and energy-efficient inference in the WI regime, making it suitable for both server and edge applications.

Keywords: Shape-based Analog computing, CMOS, machine learning, processor

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Abhishek Agwekar, Laxmi Singh. CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.. Journal of VLSI Design Tools and Technology. 2025; 15(01):8-17.
How to cite this URL:
Abhishek Agwekar, Laxmi Singh. CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.. Journal of VLSI Design Tools and Technology. 2025; 15(01):8-17. Available from: https://journals.stmjournals.com/jovdtt/article=2025/view=198472


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Regular Issue Subscription Review Article
Volume 15
Issue 01
Received 22/01/2025
Accepted 27/01/2025
Published 30/01/2025
Publication Time 8 Days
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