Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element

Year : 2025 | Volume : 15 | Issue : 01 | Page : 36 44
    By

    Shidesh S.,

  • K. B. Ramesh,

  1. Student, Department of Electronics and instrumentation Engineering, R. V. College of Engineering, Mysore Road, Bengaluru, Karnataka, India
  2. Associate Professor, Department of Electronics and instrumentation Engineering, R. V. College of Engineering, Mysore Road, Bengaluru, Karnataka, India

Abstract

Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor’s charge and discharge frequencies. To lower its latency, the C-element has additionally incorporated pull-up and pull-down routes. In contrast to other DETFFs already in use, the DETFF suggested in this study only flips once on the edge clock, significantly lowering the number of duplicated transitions brought on by glitches thus efficiently lowering power usage. The suggested DETFF and ten more DETFFs are simulated in this work using HSPICE. The results demonstrate that the suggested DETFF has obtained high performance indices in the areas of total power consumption, total power consumption with glitches and delays, and power delay product when compared to the other ten varieties of DETFFs. The suggested DETFF has reduced susceptibility to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced ageing fluctuations, according to a thorough analysis of variance.

Keywords: Double-Edge Triggered Flip-Flop (DETFF); glitch; low-power; C-element, NBTI, Power consumption, MUX

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Shidesh S., K. B. Ramesh. Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element. Journal of VLSI Design Tools and Technology. 2025; 15(01):36-44.
How to cite this URL:
Shidesh S., K. B. Ramesh. Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element. Journal of VLSI Design Tools and Technology. 2025; 15(01):36-44. Available from: https://journals.stmjournals.com/jovdtt/article=2025/view=195628


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Regular Issue Subscription Original Research
Volume 15
Issue 01
Received 16/01/2025
Accepted 20/01/2025
Published 28/01/2025
Publication Time 12 Days
251

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