RTL to GDSII Implementation UART using Verilog and Cadence tools

Year : 2025 | Volume : 15 | Issue : 01 | Page : 1 7
    By

    Dhruv Lalpurwala,

  • Vandan Parekh,

  • Robinson Paul,

  1. Student, Department of Electronics and Communication Engineering, Birla Vishvakarma Mahavidhyalaya, Anand, Gujarat, India
  2. Student, Department of Electronics and Communication Engineering, Birla Vishvakarma Mahavidhyalaya, Anand, Gujarat, India
  3. Assistant Professor, Department of Electronics and Communication Engineering, Birla Vishvakarma Mahavidhyalaya, Anand, Gujarat, India

Abstract

The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s tools in achieving a reliable and manufacturable UART design. Communicating UARTs have no shared timing system apart from the communication signal. Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse. Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly different speed than it should. Simplistic UARTs do not do this; instead, they resynchronize on the falling edge of the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.

Keywords: UART, Cadence, Verilog, Transmitter, HPC, HDL, FMSD

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Dhruv Lalpurwala, Vandan Parekh, Robinson Paul. RTL to GDSII Implementation UART using Verilog and Cadence tools. Journal of VLSI Design Tools and Technology. 2025; 15(01):1-7.
How to cite this URL:
Dhruv Lalpurwala, Vandan Parekh, Robinson Paul. RTL to GDSII Implementation UART using Verilog and Cadence tools. Journal of VLSI Design Tools and Technology. 2025; 15(01):1-7. Available from: https://journals.stmjournals.com/jovdtt/article=2025/view=193256


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Regular Issue Subscription Original Research
Volume 15
Issue 01
Received 28/12/2024
Accepted 02/01/2025
Published 09/01/2025
Publication Time 12 Days
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