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Open Access
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Sree Krishna Raja K, P. Jaya Krishna,
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- Student,, Assistant Professor, Nalla Malla Reddy Engineering College,, Nalla Malla Reddy Engineering College, Hyderabad,, Hyderabad, India, India
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Abstract
nThe performance of modern VLSI systems is heavily influenced by power constraints, necessitating precise power estimation and effective optimization techniques. Traditional methods, such as gate-level simulations, are often slow and computationally intensive. This paper introduces DRPENN (Differential Algorithm for Routing and Placement Optimization using Neural Networks), an innovative solution that combines a Switching Activity Estimator (SAE) with a neural network-assisted differential algorithm. By leveraging toggle rates from simulations to train a Graph Neural Network (GNN), DRPENN circumvents the need for extensive gate-level simulations. This trained model accurately predicts switching activity, optimizing the placement and routing of circuit elements while minimizing computational demands. The methodology involves converting gate-level netlists into graphical representations and using a differential algorithm for back-propagation. Our experimental results show that DRPENN achieves lower error rates and faster inference times compared to conventional probabilistic SAE methods, offering a promising approach for efficient and accurate VLSI design optimization.
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Keywords: VLSI design, routing optimization, placement optimization, differential algorithm, neural networks
n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools and Technology(jovdtt)]
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References
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| Volume | 14 | |
| [if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] | 02 | |
| Received | July 19, 2024 | |
| Accepted | July 31, 2024 | |
| Published | August 7, 2024 |
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