Ijvcdt Volume 01 Issue 02 2023

Regular Issue Subscription Review Article Published on :- Jan 12, 2024

Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology

Vannala Sowmya, P. Sumithabhashini,

Abstract : In this article, we’ll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) read more

[This section belongs to International Journal of VLSI Circuit Design & Technology (ijvcdt)]

29-39

Regular Issue Subscription Review Article Published on :- Jan 12, 2024

Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology

Vannala Sowmya, P. Sumithabhashini,

Abstract : In this article, we’ll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) read more

[This section belongs to International Journal of VLSI Circuit Design & Technology (ijvcdt)]

29-39

Regular Issue Subscription Original Research Published on :- Dec 04, 2023

Implementation of Adders Using Ternary Based Multiple Valued Logic

M. Mani Kumari, K. Aishwarya, B. Sukruthi,

Abstract : In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, read more

[This section belongs to International Journal of VLSI Circuit Design & Technology (ijvcdt)]

1-8

Regular Issue Subscription Original Research Published on :- Jan 05, 2024

Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology

Vannala Bhavya, K. Shyamala Murthi,

Abstract : To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be read more

[This section belongs to International Journal of VLSI Circuit Design & Technology (ijvcdt)]

10-16

Regular Issue Subscription Original Research Published on :- Jan 10, 2024

Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.

Kalvala Shylaja, M. Satya Narayana,

Abstract : In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the read more

[This section belongs to International Journal of VLSI Circuit Design & Technology (ijvcdt)]

17-28

Regular Issue Subscription Original Research Published on :- Feb 12, 2024

Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation

Malyadri Paduchur, [email protected],

Abstract : This paper introduces a novel and enhanced Gabor filter design aimed at addressing the demands of image processing applications using the Verilog read more

[This section belongs to International Journal of VLSI Circuit Design & Technology (ijvcdt)]

40-46

Editorial Board

View Full Editorial Board

ijvcdt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

Editor in Chief

Prof. Shyam Akashe, Professor and Dean ICP

ITM University Gwalior, Madhya Pradesh, India, 474001

Email :

Institutional Profile Link: https://www.itmuniversity.ac.in/about/officials

Journal: International Journal of VLSI Circuit Design & Technology

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