Study the Effect of Applied Gate Voltage on Threshold Potential and Carrier Transport Behavior of Three-Terminal Novel Prototype Device having Configuration P-type Si/SiO2/CuFeS2/Al

Year : 2026 | Volume : 03 | Issue : 02 | Page : 1 7
By

Asmita Patra,

Suman Mahata,

Animesh Layek,

  1. Research Scholar, Department of Physics, Jadavpur University, Kolkata, India
  2. Assistant Professor, Department of Physics, Jadavpur University, Kolkata, India
  3. Assistant Professor, Department of Physics, Jadavpur University, Kolkata, India

Abstract

This study presents a trial approach for the fabrication and characterization of a novel p-Si/SiO₂/CuFeS₂/Al field-dependent three-terminal electronic device designed to investigate charge transport behavior across multiple semiconductor junctions under externally applied bias voltages. The proposed prototype incorporates CuFeS₂ (chalcopyrite) as the active semiconductor layer, marking its first reported application in a field-induced electronic device architecture. The device was fabricated using a layered heterostructure consisting of p-type silicon, a silicon dioxide insulating layer, a CuFeS₂ active channel, and an aluminum electrode. Electrical characterization was performed by applying source-drain and gate bias voltages to evaluate carrier transport mechanisms, threshold voltage modulation, and field-dependent electronic response. The experimental results demonstrate that the applied gate electric field significantly influences charge carrier transport from the source to the drain, indicating effective field-controlled conduction through the heterojunction interfaces. A notable and unusual shift in the threshold voltage was observed with increasing gate voltage, suggesting the presence of interface charge trapping, field-induced band modulation, or altered carrier injection mechanisms within the CuFeS₂ layer. The observed transport characteristics reveal the potential of CuFeS₂ as a promising semiconductor material for field-effect electronic applications. The underlying physical mechanisms responsible for the electrical behavior are analyzed and discussed based on experimental observations and device architecture. This preliminary investigation establishes the feasibility of integrating CuFeS₂ into field-controlled semiconductor devices and provides valuable insights into its charge transport characteristics. The findings may contribute to the future development of novel semiconductor devices, electronic switches, sensors, and low-cost field-effect electronic components based on chalcopyrite materials.

Keywords: CuFeS2 semiconductor; Threshold potential; carrier transport mechanism; Three terminal electronic device

[This article belongs to International Journal of Crystalline Materials ]

How to cite this article: Asmita Patra, Suman Mahata, Animesh Layek. Study the Effect of Applied Gate Voltage on Threshold Potential and Carrier Transport Behavior of Three-Terminal Novel Prototype Device having Configuration P-type Si/SiO2/CuFeS2/Al. International Journal of Crystalline Materials. 2026; 03(02):1-7.
How to cite this URL: Asmita Patra, Suman Mahata, Animesh Layek. Study the Effect of Applied Gate Voltage on Threshold Potential and Carrier Transport Behavior of Three-Terminal Novel Prototype Device having Configuration P-type Si/SiO2/CuFeS2/Al. International Journal of Crystalline Materials. 2026; 03(02):1-7. Available from: https://journals.stmjournals.com/ijcm/article=2026/view=258069

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Regular Issue Subscription Original Research
Volume 03
Issue 02
Received 02/07/2026
Accepted 08/07/2026
Published 20/07/2026
Publication Time 18 Days


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