Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits

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Year : 2026 | Volume : 16 | 01 | Page :
    By

    Anupriya V,

  • Hemalatha R,

  • Kaviya Sri A,

  • Madhumitha P,

  • Nanthitha S,

  1. Assistant Professor, Sri Ramakrishna Engineering College, Coimbatore, Tamil Nadu, India
  2. Assistant Professor, PPG Institute of Technology, Coimbatore, Tamil Nadu, India
  3. Student, Sri Ramakrishna Engineering College, Coimbatore, Tamil Nadu, India
  4. Student, Sri Ramakrishna Engineering College, Coimbatore, Tamil Nadu, India
  5. Student, Sri Ramakrishna Engineering College, Coimbatore, Tamil Nadu, India

Abstract

This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis process, considering the standard working process of the circuit. Based on the simulated results, the proposed design demonstrates a significant reduction in the value of propagation delay compared with the existing CMOS inverter design, along with improved power efficiency. Transient analysis is performed under regular operating settings to evaluate the inverter’s dynamic behavior. The circuit’s switching characteristics, such as rise time, fall time, and propagation delay, can be ascertained with the aid of this analysis. According to the simulation results, compared to traditional inverter designs, the suggested CMOS inverter design significantly reduces propagation delay, improving overall speed performance. Furthermore, the leakage power analysis of the CMOS inverter circuit has been carried out under different working processes of the PMOS and NMOS devices of the circuit with improved insights into the value of the leakage current. The result proves the improved energy efficiency of the designed CMOS inverter circuit with optimal power-delay performance suitable for VLSI designs.

Keywords: CMOS Inverter, Inverter Chains, leakage power analysis, 45nm technology

How to cite this article:
Anupriya V, Hemalatha R, Kaviya Sri A, Madhumitha P, Nanthitha S. Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits. Journal of VLSI Design Tools and Technology. 2026; 16(01):-.
How to cite this URL:
Anupriya V, Hemalatha R, Kaviya Sri A, Madhumitha P, Nanthitha S. Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits. Journal of VLSI Design Tools and Technology. 2026; 16(01):-. Available from: https://journals.stmjournals.com/jovdtt/article=2026/view=239605


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Ahead of Print Subscription Review Article
Volume 16
01
Received 02/03/2026
Accepted 09/03/2026
Published 02/04/2026
Publication Time 31 Days
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