DESIGN & IMPLEMENTATION OF16-BIT MAC UNIT USING VEDIC MATHEMATICS

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Year : 2026 | Volume : 16 | 01 | Page :
    By

    K. Durga Devi,

  • B. Hema Shankar,

  • A. Phani Kumar,

  • J. Vivek,

  • Dr. T. Saran Kumar,

  • Dr. Akula pravin,

  1. UG Scholar, ECE Department, Bonam Venkata Chalamayya Engineering College(A), Odalarevu., Andhra Pradesh, India
  2. UG Scholar, ECE Department, Bonam Venkata Chalamayya Engineering College(A), Odalarevu., Andhra Pradesh, India
  3. UG Scholar, ECE Department, Bonam Venkata Chalamayya Engineering College(A), Odalarevu., Andhra Pradesh, India
  4. UG Scholar, ECE Department, Bonam Venkata Chalamayya Engineering College(A), Odalarevu., Andhra Pradesh, India
  5. Associate Professor, ECE Department, Bonam Venkata Chalamayya Engineering College(A), Odalarevu., Andhra Pradesh, India
  6. Professor, ECE Department, Bonam Venkata Chalamayya Engineering College(A), Odalarevu., Andhra Pradesh, India

Abstract

Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing delay and improving computational speed. Verilog HDL is used to describe and implement the entire architecture, guaranteeing a scalable and modular design appropriate for synthesis in contemporary VLSI systems. Simulation is used to verify the design’s functionality by testing different input combinations to confirm accuracy and performance under various operating situations. Throughput is increased by the multiplier’s integration with a 16-bit accumulator, which enables effective processing of sequential operations without the need for additional storage components. An 8-bit Vedic multiplier is integrated with a 16-bit accumulator to perform continuous multiply–accumulate operations. The design is implemented using Verilog HDL, and it is verified by simulation. The suggested architecture delivers enhanced speed, decreased propagation latency, and optimal power usage when compared to traditional MAC architecture. The design’s effectiveness and simplicity make it appropriate for contemporary real-time applications VLSI systems.

Keywords: MAC Unit, Vedic Mathematics, Urdhva Tiryagbhyam, Verilog HDL, DSP, Carry Save Adder.

How to cite this article:
K. Durga Devi, B. Hema Shankar, A. Phani Kumar, J. Vivek, Dr. T. Saran Kumar, Dr. Akula pravin. DESIGN & IMPLEMENTATION OF16-BIT MAC UNIT USING VEDIC MATHEMATICS. Journal of VLSI Design Tools and Technology. 2026; 16(01):-.
How to cite this URL:
K. Durga Devi, B. Hema Shankar, A. Phani Kumar, J. Vivek, Dr. T. Saran Kumar, Dr. Akula pravin. DESIGN & IMPLEMENTATION OF16-BIT MAC UNIT USING VEDIC MATHEMATICS. Journal of VLSI Design Tools and Technology. 2026; 16(01):-. Available from: https://journals.stmjournals.com/jovdtt/article=2026/view=239604


References

1. Jithin S, Prabhu E. Parallel multiplier-accumulator unit based on Vedic Mathematics. ARPN journal of engineering and applied sciences. 2015 May;9(22):3608-13.

2. Vinod YS, Kumar TS, Baboji K, Dadala VV, Kalyani K, Kammampati VR, Mahalaxmi US. Performance Analysis of Tera Hertz Frequencies on Intelligent Reflecting Surfaces for 6G Communications.

3. Dwivedi K, Sharma RS, Chunduri A. Hybrid multiplier-based optimized MAC unit. In2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT) 2018 Jul 10 (pp. 1-4). IEEE.

4. Kumar TS, Siddani DP, Rao IR, Harika P, Vijjapu A, Kumar GP, Satyanarayana BV. Low power adder circuit design and implementation using LECTOR technique. InInternational Conference on Cognitive Computing and Cyber Physical Systems 2024 Apr 4 (pp. 159-170). Cham: Springer Nature Switzerland.

5. Gadakh SN, Khade A. Design and optimization of 16× 16 Bit multiplier using Vedic mathematics. In2016 International Conference on Automatic Control and Dynamic Optimization Techniques (ICACDOT) 2016 Sep 9 (pp. 460-464). IEEE.

6. Bathija RK, Meena RS, Sarkar S, Sahu R. Low power high speed 16×16 bit multiplier using vedic mathematics. International Journal of Computer Applications. 2012 Jan 1;59(6).

7. Kumar ST, Kumar IG, Rao RS, Vinod YS. Design of various shaped MEMS based cantilevers executed in COMSOL multiphysics. European journal of molecular & clinical medicine. 2020;7(10):1972-9.

8. Prasanna Kumar G, Budumuru PR, Krishna Chaitanya Varma A, Satyanarayana BV, Saran Kumar T, Rao IR. Design Analysis of Memristor-Based 7T SRAM Using Heterojunction Tunneling Transistors. Journal of Circuits, Systems and Computers. 2025 Nov 30;34(17):2550280.

9. Pavan MV, Ramesh SR. An efficient booth multiplier using probabilistic approach. In2018 International Conference on Communication and Signal Processing (ICCSP) 2018 Apr 3 (pp. 0365-0368). IEEE.

10. Kumar TS, Rao IR, Vinod YS, Harika P, Satyanarayana BV, Pravin A. Area efficient and ultra low power full adder design based on GDI technique for computing systems. InInternational conference on cognitive computing and cyber physical systems 2023 Aug 4 (pp. 63-75). Cham: Springer Nature Switzerland.

Ahead of Print Subscription Review Article
Volume 16
01
Received 28/03/2026
Accepted 30/03/2026
Published 02/04/2026
Publication Time 5 Days
44

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