This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.
V. Basil Hans,
- Research Professor, Department of Commerce & Management and Humanities & Social Sciences, Srinivas University, Mangalore, Karnataka, India
Abstract
Very Large Scale Integration (VLSI) design is still one of the most active and important areas of the semiconductor industry. It is behind new developments in AI, 5G, automotive electronics, and high-performance computing. As companies like Intel, TSMC, and NVIDIA work to improve advanced-node technology, the need for qualified VLSI engineers is growing. However, people who want to work in this industry typically don’t know what technical skills, tools, and career paths they need to get there. This article gives you a clear plan for how to start a career in VLSI design. It covers the basics of digital electronics, CMOS technology, and semiconductor physics, as well as the important skills you need to know HDL languages like Verilog and SystemVerilog. It shows the VLSI design cycle, from RTL design and verification to physical design and tape-out, while also pointing out tools and methods that are important in the industry. It also talks about internship tactics, project development, certification alternatives, and new trends including low-power design, chiplet designs, and AI-driven EDA tools. The goal of this post is to give students and engineers just starting out in their careers clear, tangible steps to take to effectively enter and grow in the competitive VLSI ecosystem.
Keywords: VLSI Design, CMOS Technology, ASIC Design Flow, Verilog/SystemVerilog, and the Semiconductor Industry
V. Basil Hans. A well-planned strategy for a career path in VLSI design. Journal of VLSI Design Tools and Technology. 2026; 16(01):-.
V. Basil Hans. A well-planned strategy for a career path in VLSI design. Journal of VLSI Design Tools and Technology. 2026; 16(01):-. Available from: https://journals.stmjournals.com/jovdtt/article=2026/view=238948
References
1. Gray JP. Introduction to silicon compilation. InProceedings of the 16th Design Automation Conference 1979 Jun 25 (pp. 305-306).
2. Colocassides EM. Educational Management: Contemporary Strategic Communication Decisions for European Higher Education Institutions. International Journal of Applied Science and Engineering. 2024 Jun 1;12(1):29-45.
3. Carlson S, Gadio CT. Teacher professional development in the use of technology. Technologies for education. 2002;3(4):118-32.
4. Yıldırım B, Akcan AT, Öcal E. Teachers’ perceptions and STEM teaching activities: Online teacher professional development and employment. Journal of Baltic Science Education. 2022;21(1):84.
5. Madishetty S. Formation and characterization of n/p shallow junctions in sub-micron MOSFETs [master’s thesis]. Newark (NJ): New Jersey Institute of Technology; 2002 Aug 31.
6. Walke A, Schlenvogt G, Kurinec S. Design strategies for ultra-low power 10 nm FinFETs. Solid-State Electronics. 2017 Oct 1; 136:75-80.
7. Vedula VM. HDL slicing for verification and test [dissertation]. Austin (TX): The University of Texas at Austin; 2003. Available from: ProQuest Dissertations & Theses Global. (Publication No. 3116216).
8. Bhatt AS. A career anchor perspective of employees in a large company. InInternatio-nal Conference on Advancements in Information Technology (ICAIT) 2011 (pp. 265-270).
9. Cecchini T. Platform-based design, test and fast verification flow for mixed-signal systems on chip [PhD thesis]. Pisa (IT): University of Pisa; 2011 Apr 21
10. Liu HY. Supervised design-space exploration [dissertation]. New York (NY): Columbia University; 2015. Available from: ProQuest Dissertations & Theses Global. (Publication No. 3718005).
11. Johnsson L. VLSI architecture and design [technical report]. Pasadena (CA): California Institute of Technology; 1980 Oct. doi:10.7907/bmm7d-81×26.
12. Nemesszeghy G. USING LOGIC SYNTHESIS TOOLS FOR TEXAS INSTRUMENTS FP GAs. Periodica Polytechnica Electrical Engineering (Archives). 1994;38(2):148-74.
13. Nieman LZ, Donoghue GD, Ross LL, Morahan PS. Implementing a comprehensive approach to managing faculty roles, rewards, and development in an era of change. Academic Medicine. 1997 Jun 1;72(6):496-504.
14. Buddi N. Layout synthesis for datapath designs [master’s thesis]. Portland (OR): Portland State University; 1996. vii, 67 p. doi:10.15760/etd.7113.
15. Yang Z. A multiple-objective ILP based global routing approach for VLSI ASIC design [PhD thesis]. Waterloo (ON): University of Waterloo; 2008
16. Extending capability of formal tools: applying semiformal verification on large design [master’s thesis]. Austin (TX): University of Texas at Austin, Department of Electrical and Computer Engineering; 2019 May 10, doi:10.26153/tsw/5533.
17. Moustakas E. Design and simulation of a primitive RISC architecture using VHDL [master’s thesis]. Rochester (NY): Rochester Institute of Technology; 1991.
18. Abas MA, Zazalinda NI. Experiencing Layout Design Techniques from Highly Skilled IC Design Engineers. InAdvanced Materials and Engineering Technologies 2022 Mar 12 (pp. 283-294). Cham: Springer International Publishing.
19. Harris D. The microprocessor as a microcosm: a hands-on approach to VLSI design education. In32nd Annual Frontiers in Education 2002 Nov 6 (Vol. 3, pp. S2D-S2D). IEEE.
Journal of VLSI Design Tools and Technology
| Volume | 16 |
| 01 | |
| Received | 02/03/2026 |
| Accepted | 09/03/2026 |
| Published | 20/03/2026 |
| Publication Time | 18 Days |
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