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Aditya Chauhan,
Mitesh Limachia,
Narendra Chauhan,
Purvang Dalal,
- Student, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Associate Professor, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Assistant Professor, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Professor and Head of Department, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
Abstract
This paper surveys the architectural evolution of Reduced Instruction Set Computer (RISC) architectures from early research prototypes to modern industrial processors, tracing four decades of design refinement across academic, embedded, server, mobile, and open- hardware ecosystems. Core ISA principles, pipeline evolution, compiler–hardware co-design, and quantitative performance modeling are analyzed through four representative industrial implementations: MIPS 74K, SPARC T4, ARM Cortex-A72, and SiFive U74 (RISC-V). Each processor is examined in terms of its unique microarchitectural features, target application domain, and position within the broader instruction-count, cycle-per-instruction, and clock-period performance framework. While execution engines have evolved substantially from simple in-order pipelines toward superscalar, out-of-order, and multithreaded designs fundamental RISC characteristics such as load/store execution discipline, ISA regularity, and register-centric computation remain persistent across generations. The survey further examines emerging challenges facing high-performance RISC implementations, including speculative-execution security vulnerabilities such as Spectre and Meltdown, the growing importance of energy-proportional computing under Dark Silicon constraints, and the rise of Domain-Specific Architectures (DSAs) enabled by the open and extensible RISC-V ecosystem. Comparative tables consolidate ISA-level and microarchitectural distinctions across six representative designs, offering a structured reference for researchers and practitioners. By bridging classical RISC tenets with modern execution, security, and efficiency constraints, this work provides a comprehensive technical synthesis of how different RISC families optimized their architectures for distinct computing domains while preserving the core principles that originally defined the RISC paradigm.
Keywords: RISC, MIPS, SPARC, ARM, RISC-V, Pipeline Architecture, CPI, Load/Store Architecture.
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Journal of VLSI Design Tools and Technology
| Volume | 16 | |
| 02 | ||
| Received | 31/07/2026 | |
| Accepted | 12/08/2026 | |
| Published | 20/08/2026 | |
| Publication Time | 20 Days |