Design of Decoder Using Domino Logic Circuit for VLSI

Open Access

Year : 2023 | Volume :11 | Issue : 3 | Page : 42-51
By

    K. Rama Krishna Reddy

  1. Sai Teja Ankuru

  2. Divya Pillutla

  3. Varthya Shirisha

  1. Assistant Professor, Vasavi College of Engineering (Autonomous), Hyderabad, Telangana, India
  2. Student, Vasavi College of Engineering (Autonomous), Hyderabad, Telangana, India
  3. Student, Vasavi College of Engineering (Autonomous), Hyderabad, Telangana, India
  4. Student, Vasavi College of Engineering (Autonomous), Hyderabad, Telangana, India

Abstract

Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in many applications. For any CMOS circuit, the dissipation of power can be both static and dynamic. Dynamic dissipation in CMOS circuits occurs because of the switching of states. However, the static power dissipation is negligible in the circuit. Circuits designed using the domino model are used in various applications, like full adders, multiplexers, in memory as address selectors, comparators, and arithmetic circuits. There are different issues in domino logic circuits, namely power consumption, speed, and power delay product. A model is designed based on various approaches to solve these issues.

Keywords: Domino Logic Circuit, High speed, Low power

[This article belongs to Journal of VLSI Design Tools & Technology(jovdtt)]

How to cite this article: K. Rama Krishna Reddy, Sai Teja Ankuru, Divya Pillutla, Varthya Shirisha , Design of Decoder Using Domino Logic Circuit for VLSI jovdtt 2023; 11:42-51
How to cite this URL: K. Rama Krishna Reddy, Sai Teja Ankuru, Divya Pillutla, Varthya Shirisha , Design of Decoder Using Domino Logic Circuit for VLSI jovdtt 2023 {cited 2023 Jan 30};11:42-51. Available from: https://journals.stmjournals.com/jovdtt/article=2023/view=90626

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Regular Issue Open Access Article
Volume 11
Issue 3
Received April 25, 2022
Accepted April 30, 2022
Published January 30, 2023