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V. Anand Vardhan,
G. Naga Chaitanya,
V. Bhargav Shankar,
Harika Pangam,
Ch.Sridevi,
M.M.Vara Lakshmi,
- UG Student, Department of ECE, Bonam Venkata chalamayya Engineering college, Odalarevu, Andhra Pradesh, India
- UG Student, Department of ECE, Bonam Venkata chalamayya Engineering college, Odalarevu, Andhra Pradesh, India
- UG Student, Department of ECE, Bonam Venkata chalamayya Engineering college, Odalarevu, Andhra Pradesh, India
- Associate Professor, Department of ECE, Bonam Venkata chalamayya Engineering college, Odalarevu, Andhra Pradesh, India
- Associate Professor, Department of ECE, Bonam Venkata chalamayya Engineering college, Odalarevu, Andhra Pradesh, India
- Assistant Professor, Department of ECE, Bonam Venkata chalamayya Engineering college, Odalarevu, Andhra Pradesh, India
Abstract
CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable and high-performance systems. Moreover, the design provides enhanced noise immunity and reduced signal distortion both of which are essential for stable functioning in high-density integrated circuits. Furthermore, the suggested MVL framework aids in diminishing interconnect complexity, leading to layouts that make efficient use of area and enhancements in routing efficiency. Moreover, by optimizing the power-delay product, a well-balanced compromise between speed and energy consumption can be achieved, rendering the design highly appropriate for next-generation electronic systems. Overall, FinFET-based MVL gates provide an effective, scalable, and energy-conscious approach for future VLSI designs that tackles the basic restrictions of conventional CMOS technology while facilitating compact and high-speed circuit implementations. Moreover, the design enhances noise immunity, minimizes signal distortion, optimizes power-delay performance, improves circuit stability, and facilitates efficient, scalable, and reliable nanoscale VLSI implementations.
Keywords: Multi-Valued Logic (MVL), FinFET, Digital Circuits, VLSI Design, Low Power Circuits.
V. Anand Vardhan, G. Naga Chaitanya, V. Bhargav Shankar, Harika Pangam, Ch.Sridevi, M.M.Vara Lakshmi. High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET. Journal of Microelectronics and Solid State Devices. 2026; 13(01):-.
V. Anand Vardhan, G. Naga Chaitanya, V. Bhargav Shankar, Harika Pangam, Ch.Sridevi, M.M.Vara Lakshmi. High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET. Journal of Microelectronics and Solid State Devices. 2026; 13(01):-. Available from: https://journals.stmjournals.com/jomsd/article=2026/view=239612
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Journal of Microelectronics and Solid State Devices
| Volume | 13 |
| 01 | |
| Received | 30/03/2026 |
| Accepted | 31/03/2026 |
| Published | 02/04/2026 |
| Publication Time | 3 Days |
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