High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections.
Journal of Microelectronics and Solid State Devices
Journal of Microelectronics and Solid-State Devices [2455-3336(e)]Â is a peer-reviewed hybrid open-access journal launched in 2014 focused on the rapid publication of fundamental research papers on all areas of Solid state, Electronics, and Devices.
jomsd maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

Dr. Devendra Kr. Tripathi,, Professor
Shambhunath Institute of Engineering & Technology, Uttar Pradesh, India,
Email :
CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections.
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