Vaibhav V. Godase,
- Assistant Professor,, Department of Electronics & Telecommunication, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India
Abstract
As the proliferation of Internet of Things (IoT) devices continues to rise, there is an increasing demand for real-time, energy-efficient artificial intelligence (AI) processing directly at the network edge. Traditional edge AI accelerators, often based on deep learning models like convolutional neural networks (CNNs), struggle to meet the ultra-low-power requirements of battery-constrained IoT sensor nodes. In response to this challenge, this study introduces a neuromorphic-inspired, low-power very- large-scale integration (VLSI) architecture specifically optimized for edge AI applications in IoT environments. The proposed architecture leverages spiking neural networks (SNNs), which mimic the event-driven, asynchronous nature of biological neural systems, to drastically reduce energy consumption while maintaining accurate and responsive inference capabilities. Key innovations include the integration of biologically inspired learning mechanisms such as spike-timing-dependent plasticity (STDP), along with advanced low-power design techniques such as dynamic voltage scaling, fine-grained clock gating, and aggressive power gating. Implemented using a 22 nm CMOS process, the architecture demonstrates a five-times reduction in power consumption and a three-times improvement in energy efficiency compared to conventional CNN-based accelerators under similar workloads. Experimental results further validate its applicability to real-world edge scenarios such as environmental sensing and wearable health diagnostics. This work highlights the promise of neuromorphic computing in enabling the next generation of intelligent, autonomous, and power-aware IoT systems.
Keywords: Neuromorphic computing, low-power VLSI, event-driven processing, neuromorphic architecture
[This article belongs to Journal of Microelectronics and Solid State Devices ]
Vaibhav V. Godase. A Neuromorphic-Inspired, Low-Power VLSI Architecture for Edge AI in IoT Sensor Nodes. Journal of Microelectronics and Solid State Devices. 2025; 12(02):41-47.
Vaibhav V. Godase. A Neuromorphic-Inspired, Low-Power VLSI Architecture for Edge AI in IoT Sensor Nodes. Journal of Microelectronics and Solid State Devices. 2025; 12(02):41-47. Available from: https://journals.stmjournals.com/jomsd/article=2025/view=215197
References
1. Aral A. The promise of neuromorphic edge AI for rural environmental monitoring. Environmental Data Science. 2024 Jan; 3: e34.
2. Safa A, Van Assche J, Alea MD, Catthoor F, Gielen GG. Neuromorphic near-sensor computing: From event-based sensing to edge learning. IEEE Micro. 2022 Aug 1; 42(6): 88–95.
3. Barnell M, Raymond C, Loomis L, Isereau D, Brown D, Vidal F, Smiley S. Advanced Ultra Low- Power Deep Learning Applications with Neuromorphic Computing. In 2023 IEEE High Performance Extreme Computing Conference (HPEC). 2023 Sep 25; 1–4.
4. Mohamedyaseen A, Vasantharaj A, Kumar ES. VLSI Design of low-power edge Ai Processors for Iot devices. ICTACT J Microelectron. 2023; 9(3): 1634–1639.
5. Rocha LM, Bilgic R, Naeim M, Das S, Oprins H, Yousefzadeh A, Konijnenburg M, Milojevic D, Myers J, Ryckaert J, Biswas D. Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. IEEE Trans Very Large Scale Integr Syst. 2024 Jul 25; 32(11): 2144–2148.
6. Okonkwo JI, Abdelfattah MS, Mirtaheri P, Muhtaroglu A. Energy-aware bio-inspired spiking reinforcement learning system architecture for real-time autonomous edge applications. Front Neurosci. 2024 Sep 23; 18: 1431222.
7. Stuijt J, Sifalakis M, Yousefzadeh A, orradi F. μBrain: An event-driven and fully synthesizable architecture for spiking neural networks. Front Neurosci. 2021 May 19; 15: 664208.
8. Soman S, Suri M. Recent trends in neuromorphic engineering. Big Data Anal. 2016 Dec; 1(1): 1–19.
9. Julián P, Andreou AG, Goldberg DH. A low-power correlation-derivative CMOS VLSI circuit for bearing estimation. IEEE Trans Very Large Scale Integr Syst. 2006 Feb; 14(2): 207–12.
10. Godase V, Godase J. Diet prediction and feature importance of gut microbiome using machine learning. Evol Electr Electron Eng. 2024 Nov 6;5(2):214–9.
11. Friedman D, Heinrich H, Duan DW. A low-power CMOS integrated circuit for field-powered radio frequency identification tags. In 1997 IEEE International Solids-State Circuits Conference, Digest of Technical Papers. 1997 Feb 8; 294–295.
12. Piguet C. Low-power CMOS circuits: technology, logic design and CAD tools. CRC press; 2018 Oct 3.

Journal of Microelectronics and Solid State Devices
| Volume | 12 |
| Issue | 02 |
| Received | 21/04/2025 |
| Accepted | 30/04/2025 |
| Published | 26/05/2025 |
| Publication Time | 35 Days |
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