Design And Optimization Of High-Speed Array Multiplier

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Year : 2024 | Volume : 11 | Issue : 03 | Page :
    By

    Vaishnavi M. N,

  • K.B Ramesh,

  1. Student,, Department of Electronics and Electrical Engineering, R V College of Engineering, Mysore Rd, RV Vidyaniketan,, Post, Bengaluru, Karnataka,, India
  2. Associate Professor, Department of Electronics and Electrical Engineering, R V College of Engineering, Mysore Rd, RV Vidyaniketan,, Post, Bengaluru, Karnataka,, India

Abstract

An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel architecture minimizes computation time compared to sequential methods, making array multipliers crucial in high-performance digital systems where quick and efficient binary multiplication is essential for various applications, including arithmetic logic units and signal processing. Existing array multipliers face limitations in increased hardware complexity, resulting in longer propagation delays and higher power consumption, particularly when dealing with larger operand sizes. Their regular structures may also hinder adaptability to irregular operand sizes, restricting their scalability and applicability in modern high-performance digital systems. The proposed system introduces an innovative array multiplier design with optimized hardware complexity and enhanced adaptability. Utilizing scalable architectures and advanced circuitry, it aims to reduce propagation delays, minimize power consumption, and improve overall efficiency, overcoming the limitations of existing array multipliers in modern high-performance digital systems.

Keywords: Array Multiplier, Parallel Processing, Hardware Complexity, Propagation Delay, Power Consumption

[This article belongs to Journal of Microelectronics and Solid State Devices ]

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How to cite this article:
Vaishnavi M. N, K.B Ramesh. Design And Optimization Of High-Speed Array Multiplier. Journal of Microelectronics and Solid State Devices. 2024; 11(03):-.
How to cite this URL:
Vaishnavi M. N, K.B Ramesh. Design And Optimization Of High-Speed Array Multiplier. Journal of Microelectronics and Solid State Devices. 2024; 11(03):-. Available from: https://journals.stmjournals.com/jomsd/article=2024/view=182187


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References

  1. Rathod R, Ramesh P, Zele PS, Annapurna KY. Implementation of 32-bit complex floating point multiplier using Vedic multiplier, array multiplier and combined integer and floating point multiplier (CIFM). In2020 IEEE International Conference for Innovation in Technology (INOCON) 2020 Nov 6 (pp. 1-5). IEEE.
  2. Ravi N, Subbaiah Y, Prasad TJ, Rao TS. A novel low power, low area array multiplier design for DSP applications. In2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies 2011 Jul 21 (pp. 254-257). IEEE.
  3. Dowd PW, Bogineni K, Aly KA, Perreault JA. Hierarchical scalable photonic architectures for high-performance processor interconnection. IEEE Transactions on Computers. 1993 Sep;42(9):1105-20.
  4. Chen R, Heath RW, Andrews JG. Transmit selection diversity for unitary precoded multiuser spatial multiplexing systems with linear receivers. IEEE Transactions on Signal Processing. 2007 Feb 12;55(3):1159-71.
  5. Quinn MJ. Designing efficient algorithms for parallel computers. McGraw-Hill, Inc.; 1987 Mar 1.
  6. Thraskias CA, Lallas EN, Neumann N, Schares L, Offrein BJ, Henker R, Plettemeier D, Ellinger F, Leuthold J, Tomkos I. Survey of photonic and plasmonic interconnect technologies for intra-datacenter and high-performance computing communications. IEEE Communications Surveys & Tutorials. 2018 May 28;20(4):2758-83.
  7. Tang X, De Micheli G, Gaillardon PE. A high-performance FPGA architecture using one-level RRAM-based multiplexers. IEEE Transactions on Emerging Topics in Computing. 2016 Nov 17;5(2):210-22.
  8. Krad H, Al-Taie AY. Performance Analysis of a 32-bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Carry Adder using VHDL. Journal of Computer Science. 2022.
  9. Saha P, Banerjee A, Bhattacharyya P, Dandapat A. Improved matrix multiplier design for high‐speed digital signal processing applications. IET circuits, devices & systems. 2014 Jan;8(1):27-37.
  10. Sharma D, Rai A, Debbarma S, Prakash O, Ojha MK, Nath V. Design and optimization of 4-bit array multiplier with adiabatic logic using 65 nm CMOS technologies. IETE Journal of Research. 2023 May 4:1-4.
Regular Issue Subscription Review Article
Volume 11
Issue 03
Received 13/08/2024
Accepted 23/08/2024
Published 10/09/2024
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