An Overview on VLSI based Hardware Security in IoT Node

Notice

This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.

Year : 2026 | Volume : 04 | 01 | Page :
    By

    Kazi Kutubuddin Sayyad Liyakat,

  • Heena Shaikh,

  • Dr. Kosgiker G M,

  1. Professor and Head, Department of Electronics and Telecommunication Engineering, Brahmdevdada Mane Institute of Technology, Solapur (MS), India
  2. Asst. Professor, Department of Electronics and Telecommunication Engineering, Brahmdevdada Mane Institute of Technology, Solapur (MS), India
  3. Associate Professor, Department of Electronics and Telecommunication Engineering, Brahmdevdada Mane Institute of Technology, Solapur (MS), India

Abstract

In the coming era, security will not be a feature we add to an IoT device; it will be a property inherent to its transistor-level design. By encoding security into the VLSI architecture, we move away from the fragile “software-only” paradigm and toward a future where the identity of the device is as immutable as the laws of physics. The rapid proliferation of Internet of Things (IoT) devices has transformed global infrastructure, yet it has simultaneously exposed a critical vulnerability: the hardware layer. As IoT nodes are frequently deployed in physically insecure, remote, or hostile environments, they are uniquely susceptible to side-channel attacks, fault injection, and invasive reverse engineering. Traditional software-based security measures often prove insufficient due to their high computational overhead and vulnerability to kernel-level exploits. This paper explores the paradigm shift toward VLSI-based hardware security as the “Root of Trust” for IoT ecosystems. We examine the implementation of Physical Unclonable Functions (PUFs), hardware-based True Random Number Generators (TRNGs), and logic locking techniques embedded directly into the silicon fabric. By integrating security primitives at the architectural level, we demonstrate a methodology for achieving high-assurance cryptographic protection with minimal area, power, and latency constraints. The findings underscore that hardware-centric security is not merely an auxiliary feature but a fundamental requirement for the sustainable and secure evolution of the IoT landscape.

Keywords: VLSI, IoT, Security, Hardware Security, IoT Node security

How to cite this article:
Kazi Kutubuddin Sayyad Liyakat, Heena Shaikh, Dr. Kosgiker G M. An Overview on VLSI based Hardware Security in IoT Node. International Journal of VLSI Circuit Design & Technology. 2026; 04(01):-.
How to cite this URL:
Kazi Kutubuddin Sayyad Liyakat, Heena Shaikh, Dr. Kosgiker G M. An Overview on VLSI based Hardware Security in IoT Node. International Journal of VLSI Circuit Design & Technology. 2026; 04(01):-. Available from: https://journals.stmjournals.com/ijvcdt/article=2026/view=245121


References

  1. Liyakat KK. Transforming IoT Connectivity Through VLSI Technology. International Journal of VLSI Circuit Design & Technology. 2024;2(02):1-1.
  2. Yuan JS, Lin J, Alasad Q, Taheri S. Ultra-low-power design and hardware security using emerging technologies for Internet of Things. Electronics. 2017 Sep 8;6(3):67.
  3. Jadhav M, Nerkar PM. FPGA-Based finger vein recognition system for personal verification. Int. J. Eng. Res. Gen. Sci. 2015;3:382-8.
  4. Nerkar PM, Dhaware BU, Liyakat KS. Predictive data analytics framework based on heart healthcare system (HHS) using machine learning. Journal of Advanced Zoology. 2023;44(2).
  5. Deepa S, Kumar SP, Arun V, Lalidesh J. The Role of VLSI in Next‐Generation IoT Systems. Smart Chips for Smart Devices: VLSI Design for Next‐Generation IoT Solutions. 2026 Mar 10:249-67.
  6. Poswal R, Deshwal M, Johar AK. Review of VLSI architecture of cryptography algorithm for IoT security. InInternational Conference on Communications and Cyber Physical Engineering 2018 2024 Feb 5 (pp. 103-112). Singapore: Springer Nature Singapore.
  7. Sidhu S, Mohd BJ, Hayajneh T. Hardware security in IoT devices with emphasis on hardware trojans. Journal of Sensor and Actuator Networks. 2019 Aug 10;8(3):42.
  8. Akter S, Khalil K, Bayoumi M. A survey on hardware security: Current trends and challenges. IEEe Access. 2023 Jun 22;11:77543-65.
  9. Japa A, Majumder MK, Sahoo SK, Vaddi R, Kaushik BK. Hardware security exploiting post-CMOS devices: Fundamental device characteristics, state-of-the-art countermeasures, challenges and roadmap. IEEE Circuits and Systems Magazine. 2021 Aug 13;21(3):4-30.
  10. Knechtel J. Hardware security for and beyond CMOS technology: an overview on fundamentals, applications, and challenges. InProceedings of the 2020 International Symposium on Physical Design 2020 Mar 30 (pp. 75-86).
  11. Rose GS. Introduction: Overview of VLSI, Nanoelectronics, and Hardware Security. Security Opportunities in Nano Devices and Emerging Technologies. 2017 Nov 22:3-18.
  12. Sengupta A, Kundu S. Guest editorial securing IoT hardware: threat models and reliable, low-power design solutions. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 Nov 22;25(12):3265-7.
  13. Halak B, Zwolinski M, Mispan MS. Overview of PUF-based hardware security solutions for the Internet of Things. In2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) 2016 Oct 16 (pp. 1-4). IEEE.
  14. Hu W, Chang CH, Sengupta A, Bhunia S, Kastner R, Li H. An overview of hardware security and trust: Threats, countermeasures, and design tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2020 Dec 29;40(6):1010-38.
  15. Rajendran S, Syed A, Lourde RM. Security of an IoT network: a VLSI point of view. InInventive Communication and Computational Technologies: Proceedings of ICICCT 2019 2020 Jan 30 (pp. 789-798). Singapore: Springer Singapore.
  16. Tudosa I, Picariello F, Balestrieri E, De Vito L, Lamonaca F. Hardware security in IoT era: The role of measurements and instrumentation. In2019 II Workshop on Metrology for Industry 4.0 and IoT (MetroInd4. 0&IoT) 2019 Jun 4 (pp. 285-290). IEEE.
  17. Knechtel J. Hardware security for and beyond CMOS technology. InProceedings of the 2021 International Symposium on Physical Design 2021 Mar 22 (pp. 115-126).
  18. Dofe J, Frey J, Yu Q. Hardware security assurance in emerging IoT applications. In2016 IEEE international symposium on circuits and systems (ISCAS) 2016 May 22 (pp. 2050-2053). IEEE.
  19. Malarkodi K. VLSI Circuit Architectures for Scalable IoT Implementations. In2024 9th International Conference on Communication and Electronics Systems (ICCES) 2024 Dec 16 (pp. 127-133). IEEE.
  20. Divyanshu D, Kumar R, Khan D, Amara S, Massoud Y. Logic locking using emerging 2T/3T magnetic tunnel junctions for hardware security. Ieee Access. 2022 Sep 22;10:102386-95.
Ahead of Print Subscription Review Article
Volume 04
01
Received 16/05/2026
Accepted 22/05/2026
Published 26/05/2026
Publication Time 10 Days
1

Login


My IP

PlumX Metrics