DFT Compatible Low Power EDAC Based on Clock Gating

Year : 2025 | Volume : 03 | Issue : 01 | Page : 41 53
    By

    Hemapriya C,

  • Sananda S,

  • Sneha M.,

  • Suryakala S,

  1. Student, Department of Computer Science & Engineering, Karpagam College of Engineering, Anna University, Chennai, Tamil Nadu, India
  2. Student, Department of Computer Science & Engineering, Karpagam College of Engineering, Anna University, Chennai, Tamil Nadu, India
  3. Student, Department of Computer Science & Engineering, Karpagam College of Engineering, Anna University, Chennai, Tamil Nadu, India
  4. Student, Department of Computer Science & Engineering, Karpagam College of Engineering, Anna University, Chennai, Tamil Nadu, India

Abstract

The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction in signal control and test pattern complexity reduction. The architecture utilizes a new scan-able EDAC cell (SEDC), which can perform shift operations as a flip or time EDAC in normal operation. Specifically, with simple control signal designs, the detection logic in the proposed design can be easily controlled during scan shift operations and then captured through the global error propagation logic during test. Test pattern complexity and test time overheads depend on the proprietary EDAC structure. The SEDC designed saves 20.3% delay, 16.6% electricity, and 30.5% area from existing works.

Keywords: PVT, Technology large scale, voltage frequency, power EDAC

[This article belongs to International Journal of VLSI Circuit Design & Technology ]

How to cite this article:
Hemapriya C, Sananda S, Sneha M., Suryakala S. DFT Compatible Low Power EDAC Based on Clock Gating. International Journal of VLSI Circuit Design & Technology. 2025; 03(01):41-53.
How to cite this URL:
Hemapriya C, Sananda S, Sneha M., Suryakala S. DFT Compatible Low Power EDAC Based on Clock Gating. International Journal of VLSI Circuit Design & Technology. 2025; 03(01):41-53. Available from: https://journals.stmjournals.com/ijvcdt/article=2025/view=206718


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Regular Issue Subscription Original Research
Volume 03
Issue 01
Received 22/03/2025
Accepted 29/03/2025
Published 09/04/2025
Publication Time 18 Days
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