Reconfigurable AES Based AEAD For Multi-Mode Operation with Lightweight Compatibility

Year : 2025 | Volume : 03 | Issue : 01 | Page : 54 68
    By

    Srivinesh M,

  • Aaron Jebakumar P,

  • Apshara T,

  • Arjun K,

  1. Students, Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India
  2. Students, Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India
  3. Students, Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India
  4. Students, Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India

Abstract

The proposal is for a lightweight, multi-mode, reconfigurable authenticated encryption system with associated data (AEADs) based on AES. It is challenging to effectively integrate different AEADs in hardware because each one has its own mode of operation and/or subfunctions, even though some major AEADs share several basic components (such as the XOR-Encryption-XOR (XEX) scheme, block chaining, and advanced encryption standard (AES). This paper proposes hardware that effectively combines the basic building blocks of a cryptographic hardware (HW) accelerator for the support of various block cypher modes of the Advanced Encryption Standard (AES). They include the more intricate CBC-MAC counter, Galois counter mode, XOR-encrypt-XOR based tweaked-codebook mode with ciphertext stealing (XTS) modes, and cipher-based MAC (CMAC). Internet of Things devices can now be made more private and secure with lightweight cryptography (LWC). It is appropriate for light-weight applications with safe, minimal round operation because to the suggested reconfigurable design. The viability of the suggested hardware is proven by an adequate experimental setup for multi-mode AES-based AEADs. Consequently, the proposed hardware would then perform AES-AEADs with the same power and throughput but would only take up a substantially large lot less space than the total sum of the individual AEAD devices. The mask generator is simplified, and the parity is calculated from plaintext and related data, which is also utilized for error detection. Furthermore, the proposed hardware provides greater throughput and less energy consumption than the prior architecture.

Keywords: AEAD, Lightweight Cryptographic Algorithms, Attacks On Aes Encryption

[This article belongs to International Journal of VLSI Circuit Design & Technology ]

How to cite this article:
Srivinesh M, Aaron Jebakumar P, Apshara T, Arjun K. Reconfigurable AES Based AEAD For Multi-Mode Operation with Lightweight Compatibility. International Journal of VLSI Circuit Design & Technology. 2025; 03(01):54-68.
How to cite this URL:
Srivinesh M, Aaron Jebakumar P, Apshara T, Arjun K. Reconfigurable AES Based AEAD For Multi-Mode Operation with Lightweight Compatibility. International Journal of VLSI Circuit Design & Technology. 2025; 03(01):54-68. Available from: https://journals.stmjournals.com/ijvcdt/article=2025/view=206213


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Regular Issue Subscription Original Research
Volume 03
Issue 01
Received 22/03/2025
Accepted 29/03/2025
Published 02/04/2025
Publication Time 11 Days
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