Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology

Year : 2024 | Volume :01 | Issue : 02 | Page : 29-39
By

Vannala Sowmya

P. Sumithabhashini

  1. Student Department of Electronics and Communication Engineering, Holy Mary Institute of Technology and Science, Bogaram (v), Keesara Hyderabad India
  2. Professor Department of Electronics and Communication Engineering, Holy Mary Institute of Technology and Science, Bogaram (v), Keesara Hyderabad India

Abstract

In this article, we’ll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit’s performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the microprocessor’s ALU increases, FA efficiency must be enhanced. These results can be used to create state-of-the-art hybrid FAs with static CMOS logic, PTs, and TGs. Without the Cadence 45 nm toolkit, the FA would not exist. The reliability of the system was tested with twenty FA designs running from 0.4 V to 1.2 V. The proposed FA has been modified so that words of up to 64 bits in length may be used. The suggested FA is one of just six current systems that can continue operating at 64 bits without intermediate phase buffering. Results from simulations showing very low power usage and delay lend weight to the suggested architecture. The suggested hybrid FA circuit is a viable option for the data route design of contemporary high-performance CPUs, as shown by the simulation results. Using Mentor 16nm Technology, we successfully prototyped and tested a one-bit complete adder.

Keywords: FA, CCMOS, ALU, Microprocessor, CMOS, TGs, PTs

[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]

How to cite this article: Vannala Sowmya, P. Sumithabhashini. Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology. International Journal of VLSI Circuit Design & Technology. 2024; 01(02):29-39.
How to cite this URL: Vannala Sowmya, P. Sumithabhashini. Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology. International Journal of VLSI Circuit Design & Technology. 2024; 01(02):29-39. Available from: https://journals.stmjournals.com/ijvcdt/article=2024/view=150737



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Regular Issue Subscription Review Article
Volume 01
Issue 02
Received December 16, 2023
Accepted January 3, 2024
Published January 12, 2024
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