Omkar Tripathy,
Sritam Parida,
Bibhu Prasad Ganthia,
- Student, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
- Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
- Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
Abstract
The increasing switching frequency of modern solid-state semiconductor devices has intensified the influence of parasitic inductance, parasitic capacitance, temperature-dependent conduction losses, and transient voltage and current stresses. Conventional switching-loss models generally treat these effects independently, resulting in limited accuracy when the device operates under high-frequency and thermally varying conditions. This paper proposes a Thermo-Parasitic-Aware Adaptive Switching Model (TPASM) for coupled electrical, thermal, and parasitic analysis of high-frequency solid-state devices. The proposed formulation establishes an integrated mathematical relationship among drain current, switching-node voltage, parasitic capacitance, parasitic inductance, temperature-dependent effective resistance, switching energy, and junction temperature. A feedback relationship between power dissipation and junction temperature is incorporated to capture electro-thermal interaction during switching operation. Furthermore, a multi-objective stress function simultaneously considers normalized conduction loss, junction-temperature variation, parasitic energy, , and . The resulting formulation provides an adaptive framework for identifying operating conditions associated with excessive switching loss and device stress. The model can be implemented for Si MOSFET, SiC MOSFET, GaN HEMT, and other solid-state switching technologies. The proposed approach provides a unified mathematical basis for device-level loss prediction, thermal-stress assessment, switching- frequency selection, and reliability-oriented optimization in high-frequency microelectronic power circuits under rapidly changing load conditions while improving prediction accuracy and operational reliability.
Keywords: Solid-state devices; semiconductor switching; parasitic capacitance; parasitic inductance; electro-thermal modeling
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Journal of Microelectronics and Solid State Devices
| Volume | 13 | |
| 02 | ||
| Received | 21/09/2026 | |
| Accepted | 23/09/2026 | |
| Published | 28/09/2026 | |
| Publication Time | 7 Days |
