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Rosalin Pradhan,
Sritam Parida,
Bibhu Prasad Ganthia,
- Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
- Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
- Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
Abstract
With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach to nanoscale semiconductor devices designed for low power microelectronic applications is developed. The formulation proposed is a combination of Poisson electrostatics, carrier continuity, drift-diffusion transport, short channel effect, drain-induced barrier lowering, quantum- confinement correction and compact drain-current modelling. An electrostatic scaling length is defined to relate channel geometry to the electrostatic stability. The threshold voltage, subthreshold swing, ON/OFF current ratio, transconductance, propagation delay and power-delay product are also extracted from the model. The static and dynamic power minimization in conjunction with satisfactory current drive and leakage requirements form a multi-objective optimization problem that is developed. This mathematical framework allows for systematic analysis of the nanoscale transistor’s behaviour, and design conditions that are considered feasible for low power operation can be identified. Model can be applied to a multigate semiconductor structure such as FinFET, double- gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), nanowire FET (Field-Effect Transistor) and others. The proposed approach puts in place a theoretical basis for compact device modelling, sensitivity analysis of the device parameters and mathematical optimization of advanced microelectronic devices.
Keywords: Nanoscale semiconductor devices; mathematical modelling; FinFET; MOSFET; short- channel effects; leakage current; low-power microelectronics; electrostatic scaling
[This article belongs to Journal of Microelectronics and Solid State Devices ]
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Journal of Microelectronics and Solid State Devices
| Volume | 13 | |
| Issue | 02 | |
| Received | 18/09/2026 | |
| Accepted | 19/09/2026 | |
| Published | 26/09/2026 | |
| Publication Time | 8 Days |