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Maitra Shah,
Mitesh Limachia,
Narendra Chauhan,
Sagar Kavaiya,
Purvang Dalal,
- Student, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Associate Professor, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Assistant Professor, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Assistant Professor, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
- Professor and Head, Department of Electronics and Communication Engineering, Dharmsinh Desai University, Nadiad, Gujarat, India
Abstract
As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed using Icarus Verilog and GTKWave. The baseline implementation occupied a die area of 147 μm × 147 μm with a core utilization of 65%. The design successfully passed all physical verification stages, including Design Rule Check (DRC), Layout Versus Schematic (LVS), and timing analysis. To investigate the impact of area optimization, the die dimensions were reduced to 75 μm × 75 μm, and the core utilization was increased to 85%. Experimental results demonstrate that the optimized design achieved a maximum operating frequency of 1.09 GHz, compared with 820 MHz for the baseline implementation, representing an improvement of approximately 33%. Furthermore, total power consumption decreased significantly from 113 μW to 43.5 μW, resulting in a power reduction of nearly 61.5%. However, the increased placement density also led to higher routing congestion and greater implementation complexity, highlighting the inherent trade-offs among performance, power, area, and routability. The results demonstrate that open-source EDA tools and the SkyWater 130 nm PDK provide a reliable and reproducible platform for evaluating physical design methodologies. The presented implementation establishes a useful baseline for future research on automated VLSI design flows and optimization techniques targeting power, performance, and area (PPA).
Keywords: RTL-to-GDSII, Physical Design, SkyWater 130nm PDK, Static Timing Analysis, PPA Optimization, Antenna Effect Mitigation.
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| Volume | 04 | |
| 02 | ||
| Received | 30/07/2026 | |
| Accepted | 19/08/2026 | |
| Published | 22/08/2026 | |
| Publication Time | 23 Days |