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V.Ratna Rajeswari Sri Vidya,
S.Veera Venkata Gopala Krishna,
T.Venkateswari,
Y.Venkata Satya Krishna,
T.Hemanth,
Dr BSD SARMA KOMPELLA,
- UG Scholar, Department of ECE, Bonam venkata chalamayya, Engineering College, Autonomous Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of ECE, Bonam venkata chalamayya Engineering College, Autonomous Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of ECE, Bonam venkata chalamayya Engineering College, Autonomous Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of ECE, Bonam venkata chalamayya Engineering College, Autonomous Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of ECE, Bonam venkata chalamayya Engineering College, Autonomous Odalarevu, Andhra Pradesh, India
- Professor, Department of ECE, Bonam venkata chalamayya Engineering College, Autonomous, Odalarevu, Andhra Pradesh, India
Abstract
Secure data transmission has become increasingly important with the rapid growth of digital communication and embedded systems. Protecting sensitive information from unauthorized access requires reliable cryptographic solutions. Among the available techniques, the Advanced Encryption Standard (AES) is widely recognized for its strong security and efficient implementation in both hardware and software environments. In this work, the design and performance evaluation of an AES-based crypto processor with LFSR-driven key expansion is presented for VLSI applications. Unlike the conventional key scheduling approach, the proposed method utilizes a Linear Feedback Shift Register (LFSR) to generate round keys in a hardware-efficient manner. The design is modeled using Verilog HDL and validated through simulation using Xilinx Vivado. The proposed architecture emphasizes both structural design optimization and performance improvement. Experimental results indicate a reduction in hardware complexity along with enhancements in speed and power efficiency. These characteristics make the design suitable for FPGA-based secure systems and resource-constrained embedded applications. The suggested design shows enhanced scalability and flexibility, allowing it to accommodate various key sizes and encryption needs. Utilizing LFSR also diminishes computational overhead, which helps to reduce latency and promote effective hardware use. Moreover, synthesis outcomes validate superior area-delay performance in comparison to conventional AES implementations.
Keywords: AES, LFSR, Cryptography, FPGA, VLSI, Verilog HDL
V.Ratna Rajeswari Sri Vidya, S.Veera Venkata Gopala Krishna, T.Venkateswari, Y.Venkata Satya Krishna, T.Hemanth, Dr BSD SARMA KOMPELLA. Performance Analysis of AES Encryption Using LFSR-Based Key Expansion in VLSI. Recent Trends in Electronics Communication Systems. 2026; 13(01):-.
V.Ratna Rajeswari Sri Vidya, S.Veera Venkata Gopala Krishna, T.Venkateswari, Y.Venkata Satya Krishna, T.Hemanth, Dr BSD SARMA KOMPELLA. Performance Analysis of AES Encryption Using LFSR-Based Key Expansion in VLSI. Recent Trends in Electronics Communication Systems. 2026; 13(01):-. Available from: https://journals.stmjournals.com/rtecs/article=2026/view=240291
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Recent Trends in Electronics Communication Systems
| Volume | 13 |
| 01 | |
| Received | 02/04/2026 |
| Accepted | 04/04/2026 |
| Published | 18/04/2026 |
| Publication Time | 16 Days |
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