Manas Kumar Yogi,
- Assistant Professor, CSE Department Pragati University, Andhra Pradesh, India
Abstract
Modern chip multiprocessors increasingly rely on many-core arrays to accelerate dense linear algebra kernels such as block-level general matrix multiplication (GEMM), where inter-tile communication often rivals computation cost. Network-on-Chip (NoC) topology therefore strongly influences overall latency and energy efficiency. This work proposes a mirror-symmetric NoC topology for 64-core arrays, in which long-range bypass links are added about a central reflective axis to shorten paths between symmetric core partitions that frequently exchange matrix tiles during blocked GEMM execution. Using a cycle-accurate interconnection simulator calibrated with a 45 nm energy model, the mirror-symmetric topology is compared against conventional 2D mesh and 2D torus networks under synthetic and GEMM-derived traffic across varying injection loads and block sizes. Results show the mirror-symmetric design reduces average packet latency by up to 24% relative to mesh and up to 9% relative to torus at moderate-to-high loads, while consuming 14-19% less energy per flit than torus and remaining close to mesh-level energy. The proposed topology achieves the lowest energy-delay product among the three designs across all tested block sizes, indicating that symmetry-aware link placement offers a favorable latency-energy balance for matrix-multiplication-dominated many-core workloads.
Keywords: Network-on-Chip, mirror-symmetric topology, mesh, torus, block matrix multiplication, latency, energy-delay product, many-core architecture
[This article belongs to Journal of Operating Systems Development & Trends ]
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Journal of Operating Systems Development & Trends
| Volume | 13 | |
| Issue | 02 | |
| Received | 26/08/2026 | |
| Accepted | 03/09/2026 | |
| Published | 08/10/2026 | |
| Publication Time | 43 Days |