Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design

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This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.

Year : 2026 | Volume : 04 | 01 | Page :
    By

    Rosalin Pradhan,

  • Bibhu Prasad Ganthia,

  1. Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India
  2. Assistant Professor, Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal, Odisha, India

Abstract

The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage timing estimation and reduce optimization overhead. The proposed methodology integrates supervised machine learning algorithms with physical design parameters including routing congestion, net length, fan-out, switching activity, and placement density to predict potential timing violations before final signoff analysis. A dataset generated from multiple benchmark circuits is utilized for training and validation using Random Forest, XGBoost, and Deep Neural Network models. The developed framework demonstrates higher prediction accuracy and faster analysis compared with conventional timing verification approaches. Experimental evaluation indicates that the proposed model achieves prediction accuracy above 96%, while reducing timing analysis runtime by nearly 38% in complex VLSI layouts. The framework further assists designers in identifying critical paths and optimization hotspots during early physical design stages. The proposed approach provides an intelligent, scalable, and computationally efficient solution for next-generation nanoscale VLSI system design.

Keywords: Sub-7nm VLSI Design, Timing Violation Prediction, Machine Learning, Physical Design Automation, Static Timing Analysis, Deep Neural Networks.

How to cite this article:
Rosalin Pradhan, Bibhu Prasad Ganthia. Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design. International Journal of VLSI Circuit Design & Technology. 2026; 04(01):-.
How to cite this URL:
Rosalin Pradhan, Bibhu Prasad Ganthia. Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design. International Journal of VLSI Circuit Design & Technology. 2026; 04(01):-. Available from: https://journals.stmjournals.com/ijvcdt/article=2026/view=243973


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Ahead of Print Subscription Review Article
Volume 04
01
Received 12/05/2026
Accepted 14/05/2026
Published 15/05/2026
Publication Time 3 Days
1

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