Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation

Year : 2026 | Volume : 13 | Issue : 01 | Page : 10 19
By

Amit Pandhare,

Aditya Kumbhar,

Vaibhav Godase,

  1. Student, Department of Electronics and Telecommunication Engineering, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India
  2. student, Department of Electronics and Telecommunication Engineering, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India
  3. Assistant Professor, Department of Electronics and Telecommunication Engineering, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India

Abstract

This paper presents a machine learning (ML) assisted framework for the multi-objective optimization of nanoscale bulk n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with a 10 nm physical gate length, high-k HfO₂ gate dielectric, and TiN metal gate. Technology computer-aided design (TCAD) simulations employing drift-diffusion transport, Shockley-Read-Hall recombination, Lombardi mobility degradation, and density- gradient quantum correction models are used to generate a parametric dataset of 2,400 device configurations spanning gate length (L₝), equivalent oxide thickness (EOT), channel doping (Nₐʰ), and source/drain peak doping (Nₛᵈ). Key s of merit—threshold voltage (Vₜʰ), subthreshold swing (SS), drain-induced barrier lowering (DIBL), and I₀ₙ/I₀ᵄᵄ ratio—are extracted from simulated Iᵈ-Vᵍ and Iᵈ-Vᵈ characteristics. An artificial neural network (ANN) and a random forest (RF) regressor are trained on this dataset. The ANN achieves a coefficient of determination R² of 0.9931 for Vₜʰ prediction and 0.9887 for SS, with root-mean-square errors of 4.2 mV and 1.8 mV/decade, respectively. The RF model attains comparable accuracy with superior interpretability via feature importance scores, identifying EOT and Nₐʰ as the dominant parameters governing electrostatic integrity. Bayesian-guided surrogate optimization using the trained ANN converges to a Pareto-optimal design with Vₜʰ = 0.38 V, SS = 71 mV/dec, DIBL = 42 mV/V, and I₀ₙ/I₀ᵄᵄ = 1.6 × 10⁷ in under 90 seconds—a 340× speedup relative to exhaustive TCAD sweeps. The methodology is scalable to FinFET and gate-all-around (GAA) architectures and provides a robust, physics-informed pathway for compact device co- optimization.

Keywords: MOSFET optimization, TCAD simulation, machine learning, artificial neural network, random forest, subthreshold swing, DIBL, high-k dielectric, and device parameter extraction.

[This article belongs to Journal of Microelectronics and Solid State Devices ]

How to cite this article: Amit Pandhare, Aditya Kumbhar, Vaibhav Godase. Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation. Journal of Microelectronics and Solid State Devices. 2026; 13(01):10-19.
How to cite this URL: Amit Pandhare, Aditya Kumbhar, Vaibhav Godase. Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation. Journal of Microelectronics and Solid State Devices. 2026; 13(01):10-19. Available from: https://journals.stmjournals.com/jomsd/article=2026/view=238972

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Regular Issue Subscription Review Article
Volume 13
Issue 01
Received 25/02/2026
Accepted 27/02/2026
Published 20/03/2026
Publication Time 23 Days

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