Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices

Year : 2025 | Volume : 03 | Issue : 02 | Page : 23 34
    By

    Bhima Shankar Kumbhar,

  • Rohidas Kendre,

  • Vaibhav Godase,

  1. Student, Department of Electronics & Telecommunication Engineering, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India
  2. Student, Department of Electronics & Telecommunication Engineering, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India
  3. Assistant Professor, Department of Electronics & Telecommunication Engineering, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India

Abstract

The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle to meet the low-power and high-performance requirements of battery-operated IoT systems. To address these limitations, this paper presents a low-power reconfigurable finite impulse response (FIR) digital filter architecture optimized for FPGA-based edge environments. The proposed design leverages distributed arithmetic to eliminate the use of power-hungry multipliers, incorporates coefficient symmetry and pipelining to minimize logic activity, and integrates dynamic partial reconfiguration to support real-time adaptability without requiring full hardware resynthesis. The architecture is implemented and evaluated on a Xilinx Artix-7 FPGA platform using real- world sensor inputs from temperature and vibration modules. Experimental results demonstrate a 42.7 percent reduction in total power consumption, a 31.4 percent reduction in LUT utilization, and an 18.3 percent improvement in maximum operating frequency compared to conventional multiplier-based FIR designs. The reconfiguration mechanism enables seamless modification of filter order and coefficients, significantly enhancing flexibility for dynamic IoT environments. These results confirm that the proposed architecture offers a robust, energy-efficient, and scalable solution for next-generation IoT edge devices requiring real-time digital signal processing.

Keywords: Low-power design; FPGA; distributed arithmetic; reconfigurable digital filter; IoT edge devices; partial reconfiguration; signal processing architecture.

[This article belongs to International Journal of VLSI Circuit Design & Technology ]

How to cite this article:
Bhima Shankar Kumbhar, Rohidas Kendre, Vaibhav Godase. Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices. International Journal of VLSI Circuit Design & Technology. 2025; 03(02):23-34.
How to cite this URL:
Bhima Shankar Kumbhar, Rohidas Kendre, Vaibhav Godase. Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices. International Journal of VLSI Circuit Design & Technology. 2025; 03(02):23-34. Available from: https://journals.stmjournals.com/ijvcdt/article=2025/view=235617


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Regular Issue Subscription Original Research
Volume 03
Issue 02
Received 25/11/2025
Accepted 05/12/2025
Published 31/12/2025
Publication Time 36 Days
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