Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed

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Year : August 7, 2024 at 4:14 pm | [if 1553 equals=””] Volume :14 [else] Volume :14[/if 1553] | [if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] : 02 | Page : 1-13

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Ayushi Vinodia, Kanchan Cecil,

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  1. Student,, Professor, Jabalpur Engineering College,, Jabalpur Engineering College, Madhya Pradesh,, Madhya Pradesh, India, India
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Abstract

nThis paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces read and write delays, outperforming traditional 6T, RHRD-12T, SEUH-12T, and NHRC-14T SRAM cells. Specifically, the HS-14T demonstrates an impressive 80% reduction in read delay compared to NHRC-14T, an 88% reduction compared to RHRD-12T, and an 89% reduction compared to SEUH-14. In terms of write delay, the HS-14T shows a 66% reduction compared to NHRC-14T, a 98.75% reduction compared to RHRD-12T, and a 25% reduction compared to SEUH-14. Additionally, the HS-14T exhibits an 18% decrease in leakage current compared to RHRD-12T and a 1.63% decrease compared to SUEH-12T, though it shows a 55% increase compared to NHRC-14T. The software used for simulations is Symica DE, and the technology node is 45 nm. This study highlights the HS-14T SRAM’s potential for significantly enhanced performance and productivity in various computing systems, making it a compelling choice for applications where rapid data access and energy efficiency are paramount.

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Keywords: SRAM cell, read delay, write delay leakage current, Symica DE, minicomputers, cache memory

n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools and Technology(jovdtt)]

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[/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue under section in Journal of VLSI Design Tools and Technology(jovdtt)][/if 424][if 424 equals=”Conference”]This article belongs to Conference [/if 424]

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How to cite this article: Ayushi Vinodia, Kanchan Cecil. Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed. Journal of VLSI Design Tools and Technology. August 7, 2024; 14(02):1-13.

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How to cite this URL: Ayushi Vinodia, Kanchan Cecil. Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed. Journal of VLSI Design Tools and Technology. August 7, 2024; 14(02):1-13. Available from: https://journals.stmjournals.com/jovdtt/article=August 7, 2024/view=0

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[if 424 not_equal=””]Regular Issue[else]Published[/if 424] Subscription Original Research

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Journal of VLSI Design Tools and Technology

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[if 344 not_equal=””]ISSN: 2249-474X[/if 344]

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Volume 14
[if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] 02
Received July 5, 2024
Accepted July 24, 2024
Published August 7, 2024

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