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Banoth Krishna, Sandeep Singh Gill, Amod Kumar
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- Research Scholar, Professor, Professor and Head Department of Electrical Engineering, National Institute of Technical Teachers Training and Research, Chandigarh, Department of Electrical Engineering, National Institute of Technical Teachers Training and Research, Chandigarh, Department of Electrical Engineering, National Institute of Technical Teachers Training and Research, Chandigarh Punjab, Punjab, Punjab India, India, India
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Abstract
nThis paper focuses on the design and optimization of latch comparators for high-speed data converter applications. The performance of different comparator architectures is compared in terms of speed, power consumption, and noise performance. The proposed latch comparator architecture uses a preamplifier to boost gain and sensitivity, and a latch to store the output signal. The latch comparator design is optimized for low power consumption and high speed, and is implemented using 180 nm CMOS technology. The circuits are simulated using cadence virtuoso simulators with a 1.8 V supply DC voltage and a clock frequency of approximately 500 MHz. The responses of the circuits are analyzed and plotted, and the static and dynamic characteristics of different types of comparators are compared, highlighting their advantages and disadvantages. Simulation results show that the proposed latch comparator architecture has better performance compared to other comparator architectures, with lower power consumption and higher speed. The paper also discusses the trade-offs between power consumption, speed, and noise performance, and provides guidelines for selecting the appropriate comparator architecture for high-speed data converter applications.
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Keywords: High speed comparator, Latch comparator, Double tail comparator, High speed ADC
n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools and Technology(jovdtt)]
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References
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- Babayan-Mashhadi, S., & Lotfi, R. (2013). Analysis and design of a low-voltage low-power double-tail comparator. IEEE transactions on very large-scale integration (vlsi) systems, 22(2), 343-352.
- Yaqubi, E., & Zahiri, S. H. (2017). Optimum design of a double-tail latch comparator on power, speed, offset and size. Analog Integrated Circuits and Signal Processing, 90(2), 309-319.
- Purushothaman, A., & Parikh, C. D. (2015). A new delay model and geometric programming-based design automation for latched comparators. Circuits, Systems, and Signal Processing, 34(9), 2749-2764.
- Bahmanyar, P., Maymandi-Nejad, M., Hosseini-Khayat, S., & Berekovic, M. (2016). Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications. Analog Integrated Circuits and Signal Processing, 86(2), 159-169.
- Jain, R., Dubey, A. K., Varshney, V., & Nagaria, R. K. (2017, October). Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure. In 2017 4th IEEE Uttar Pradesh section international conference on electrical, computer and electronics (UPCON) (pp. 217-222). IEEE.
- Dubey, A. K., & Nagaria, R. K. (2018). Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load. Microelectronics Journal, 78, 1-10.
- Varshney, V., & Nagaria, R. K. (2020). Design and analysis of ultra-high-speed low-power double tail dynamic comparator using charge sharing scheme. AEU-International Journal of Electronics and Communications, 116, 153068.
- Dubey, A. K., & Nagaria, R. K. (2019). Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage. Analog Integrated Circuits and Signal Processing, 101(2), 307-317.
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| Volume | 14 | |
| [if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] | 01 | |
| Received | May 16, 2024 | |
| Accepted | May 23, 2024 | |
| Published | May 30, 2024 |
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n function myFunction2() {n var x = document.getElementById(“browsefigure”);n if (x.style.display === “block”) {n x.style.display = “none”;n }n else { x.style.display = “Block”; }n }n document.querySelector(“.prevBtn”).addEventListener(“click”, () => {n changeSlides(-1);n });n document.querySelector(“.nextBtn”).addEventListener(“click”, () => {n changeSlides(1);n });n var slideIndex = 1;n showSlides(slideIndex);n function changeSlides(n) {n showSlides((slideIndex += n));n }n function currentSlide(n) {n showSlides((slideIndex = n));n }n function showSlides(n) {n var i;n var slides = document.getElementsByClassName(“Slide”);n var dots = document.getElementsByClassName(“Navdot”);n if (n > slides.length) { slideIndex = 1; }n if (n (item.style.display = “none”));n Array.from(dots).forEach(n item => (item.className = item.className.replace(” selected”, “”))n );n slides[slideIndex – 1].style.display = “block”;n dots[slideIndex – 1].className += ” selected”;n }n”}]