A Majority Function Based Full Subtractor

Year : 2024 | Volume : 13 | Issue : 02 | Page : 8 14
    By

    Angshuman Chakraborty,

  • Tanmoy Baraj,

  1. Associate Professor, Department of Electronics and Communication, Tripura Institute of Technology, Tripura, India
  2. Research Scholar, Department of Electronics and Communication, Tripura Institute of Technology, Tripura, India

Abstract

In the present landscape of very large-scale integration (VLSI) technology, the imperative to implement Boolean functions with minimal gate count remains a cornerstone of efficient circuit design. This pursuit has only grown more critical with the evolution of low-power design strategies, which now offer significantly enhanced benefits compared to traditional approaches. The trifecta of performance, affordability, and dependability continue to drive innovation in this field, shaping the trajectory of technological advancements across various sectors. Of particular importance is the escalating recognition of power dissipation as a pivotal factor in shaping competitive markets, such as those for wireless applications, laptops, and portable medical equipment. As consumer demand for efficiency and longevity in battery-powered devices intensifies, reducing power consumption has become synonymous with improving product usability and market competitiveness. This paper contributes to this ongoing discourse by focusing on the comparative analysis of multiple full subtractor circuits, evaluating their transistor count and overall power consumption. Central to our investigation is the introduction of a novel full subtractor design based on majority logic, which promises substantial advancements over established methodologies. By leveraging the inherent advantages of majority logic, our proposed circuit aims to streamline operations, minimize gate complexity, and ultimately enhance power efficiency—a critical consideration in contemporary VLSI design paradigms. Through meticulous experimentation and comparative study, we highlight the distinct advantages of our proposed majority logic-based full subtractor. Not only does it exhibit a reduced transistor count and lower power consumption compared to traditional designs, but it also demonstrates robust performance metrics across varying operational conditions

Keywords: VLSI, majority function, leakage power, MTCMOS, threshold

[This article belongs to Research & Reviews : Journal of Physics ]

How to cite this article:
Angshuman Chakraborty, Tanmoy Baraj. A Majority Function Based Full Subtractor. Research & Reviews : Journal of Physics. 2024; 13(02):8-14.
How to cite this URL:
Angshuman Chakraborty, Tanmoy Baraj. A Majority Function Based Full Subtractor. Research & Reviews : Journal of Physics. 2024; 13(02):8-14. Available from: https://journals.stmjournals.com/rrjophy/article=2024/view=206369


References

    1. Chakraborty A, Pradhan SN. A new design of adder circuit for low power and high speed in sub-threshold region. Int J Electron Lett. 2014;2:17–29. DOI: 10.1080/21681724.2013.860575.
    2. Mahaboobbasha M, Venkataramanaiah K, Reddy PR. Low Area–High Speed–Energy EfficientOne Bit Full SubtractorWithMTCMOS. International Journal of Applied Engineering Research. 2015;10(11):27593-604.
    3. Monikashree TS, Divya A, Kesthara V, Nithya Shree S. Area efficient full subtractor design using CMOS technology. Int J Sci Eng Technol Res. 2014;2(4):ISSN: 2320–8945.
    4. Gautam M, Akashe S. Reduction of leakage current and power in full subtractor using MTCMOS technique. In: International Conference on Computer Communication and Informatics. IEEE Publications; 2013. p. 1–4. DOI: 10.1109/ICCCI.2013.6466143.
    5. Chander P, et al. VLSI design of full subtracter using multi-threshold CMOS to reduce the leakage power and ground. 2015.
    6. Babu KP, Basha SA, Devanna H. Design of low power CMOS full subtracter. IJISET-Int J Innov Sci Eng Technol. 2014;1.
    7. Basha MM, Ramanaiah KV, Reddy PR. Design of CMOS full subtractor using 10T for object detection application. Int J Reasoning-Based Intell Syst. 2018;10:286–95. DOI: 10.1504/IJRIS.2018.096223.
    8. Gupta R, Gupta R, Sharma S. High performance full subtractor using floating-gate MOSFET. Microelectron Eng. 2016;162:75–8. DOI: 10.1016/j.mee.2016.05.011.
    9. Dhar K, Chatterjee A, Chatterjee S. Design of an energy efficient, high speed, low power full subtractor using GDI technique. In: IEEE Students’ Technology Symposium. IEEE Publications; 2014. p. 199–204. DOI: 10.1109/TechSym.2014.6808046.
    10. Haghparast B, Navi K, Majid N, Daraeizadeh S, Nejad K. A novel current mode full adder based on majority function. World Appl Sci J. 2008;4:676–80.
    11. Navi K, Maeen M, Hashemipour O. An energy efficient full adder cell for low voltage. IEICE Electron Express. 2009;6:553–9. DOI: 10.1587/elex.6.553.

     

Regular Issue Subscription Original Research
Volume 13
Issue 02
Received 01/07/2024
Accepted 08/07/2024
Published 10/07/2024
Publication Time 9 Days
195

Login


My IP

PlumX Metrics