Custom Back-Side Illuminated Frame Transfer Charge Coupled Device (CCD): Chip Design and Electro-Optical Characterization

Open Access

Year : 2025 | Volume : 12 | Issue : 03 | Page : 39 55
    By

    Ayush Kumar,

  • Parul Singh,

  • Vishal Indubhai Sakarvadiya,

  • Arti Sarkar,

  • Somya S Sarkar,

  1. Scientist, Space Application Centre, Indian Space Research Organization, Ahmedabad, Gujarat, India
  2. Scientist, Space Application Centre, Indian Space Research Organization, Ahmedabad, Gujarat, India
  3. Scientist, Space Application Centre, Indian Space Research Organization, Ahmedabad, Gujarat, India
  4. Group Director, Space Application Centre, Indian Space Research Organization, Ahmedabad, Gujarat, India
  5. Deputy Director, Space Application Centre, Indian Space Research Organization, Ahmedabad, Gujarat, India

Abstract

This paper provides a comprehensive overview of the chip design and electro-optical characterization of a Charge Coupled Device (CCD). While CCD technology is well-established, there are limited research articles that offer holistic perspective of CCD chip development, covering aspects ranging from device architecture and chip layout design to characterization and optimization of electro-optical parameters. In this paper, we present CCD chip design and characterization of a custom 1200 x 256 pixels, frame transfer, Back Side Illuminated (BSI) device. The photosensitive pixels in this device have two phase architecture with 32 μm x 32 μm pixel size and shielded anti-blooming to prevent charge spill-over after saturation. The device architecture and design optimization at block level as well as full chip level are presented to achieve the targeted device performance. Furthermore, device electro-optical performance evaluation, characterization and optimization of Chip-On-Board (COB) packaged detector is also presented in this paper. While the COB level evaluation of detector performance parameters aligns closely with the designed values, problem was encountered concerning the lower Full Well Capacity (FWC). A unique method was used to investigate the FWC limiting section utilizing signal charge binning. The substrate bounce is identified as a root cause for lower FWC and by clock level optimization, targeted FWC is achieved.

Keywords: CCD, BSI, Charge Binning, FWC, Substrate Bounce, chip design, characterization

[This article belongs to Journal of Semiconductor Devices and Circuits ]

How to cite this article:
Ayush Kumar, Parul Singh, Vishal Indubhai Sakarvadiya, Arti Sarkar, Somya S Sarkar. Custom Back-Side Illuminated Frame Transfer Charge Coupled Device (CCD): Chip Design and Electro-Optical Characterization. Journal of Semiconductor Devices and Circuits. 2025; 12(03):39-55.
How to cite this URL:
Ayush Kumar, Parul Singh, Vishal Indubhai Sakarvadiya, Arti Sarkar, Somya S Sarkar. Custom Back-Side Illuminated Frame Transfer Charge Coupled Device (CCD): Chip Design and Electro-Optical Characterization. Journal of Semiconductor Devices and Circuits. 2025; 12(03):39-55. Available from: https://journals.stmjournals.com/josdc/article=2025/view=218105


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Regular Issue Open Access Original Research
Volume 12
Issue 03
Received 11/07/2025
Accepted 17/07/2025
Published 26/07/2025
Publication Time 15 Days
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